
Tri M. Hoang
Examiner (ID: 17092, Phone: (571)270-1515 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 731 |
| Issued Applications | 674 |
| Pending Applications | 0 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15249775
[patent_doc_number] => 10510415
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-12-17
[patent_title] => Memory device using comb-like routing structure for reduced metal line loading
[patent_app_type] => utility
[patent_app_number] => 16/165660
[patent_app_country] => US
[patent_app_date] => 2018-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8650
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165660
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/165660 | Memory device using comb-like routing structure for reduced metal line loading | Oct 18, 2018 | Issued |
Array
(
[id] => 14587335
[patent_doc_number] => 20190221276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => NOVEL MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/159214
[patent_app_country] => US
[patent_app_date] => 2018-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8188
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159214
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159214 | Memory device | Oct 11, 2018 | Issued |
Array
(
[id] => 15775203
[patent_doc_number] => 20200118619
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => APPARATUS FOR DEEP LEARNING OPERATIONS ON RESISTIVE CROSSBAR ARRAY
[patent_app_type] => utility
[patent_app_number] => 16/159211
[patent_app_country] => US
[patent_app_date] => 2018-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3984
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159211
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/159211 | Apparatus for deep learning operations on resistive crossbar array | Oct 11, 2018 | Issued |
Array
(
[id] => 13878277
[patent_doc_number] => 20190035479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-31
[patent_title] => BACKUP POWER CIRCUIT AND ELECTRICAL DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/146946
[patent_app_country] => US
[patent_app_date] => 2018-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6477
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146946
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/146946 | Backup power circuit and electrical device | Sep 27, 2018 | Issued |
Array
(
[id] => 15822537
[patent_doc_number] => 10636460
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Semiconductor system including mode register control circuit
[patent_app_type] => utility
[patent_app_number] => 16/144298
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6125
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144298
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/144298 | Semiconductor system including mode register control circuit | Sep 26, 2018 | Issued |
Array
(
[id] => 14888635
[patent_doc_number] => 10424364
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-09-24
[patent_title] => Memory device and control method thereof
[patent_app_type] => utility
[patent_app_number] => 16/144172
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3480
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144172
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/144172 | Memory device and control method thereof | Sep 26, 2018 | Issued |
Array
(
[id] => 15732931
[patent_doc_number] => 10614898
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-04-07
[patent_title] => Adaptive control of memory cell programming voltage
[patent_app_type] => utility
[patent_app_number] => 16/143916
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 14177
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143916
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/143916 | Adaptive control of memory cell programming voltage | Sep 26, 2018 | Issued |
Array
(
[id] => 14572953
[patent_doc_number] => 20190214084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => VARIABLY RESISTIVE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/139762
[patent_app_country] => US
[patent_app_date] => 2018-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6719
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139762
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/139762 | Variably resistive memory device | Sep 23, 2018 | Issued |
Array
(
[id] => 14109601
[patent_doc_number] => 20190096476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => Low Voltage Bit-Cell
[patent_app_type] => utility
[patent_app_number] => 16/138250
[patent_app_country] => US
[patent_app_date] => 2018-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7212
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138250
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/138250 | Low voltage bit-cell | Sep 20, 2018 | Issued |
Array
(
[id] => 15687507
[patent_doc_number] => 20200098417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => MEMORY DEVICE WITH IMPROVED WRITING FEATURES
[patent_app_type] => utility
[patent_app_number] => 16/138346
[patent_app_country] => US
[patent_app_date] => 2018-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6528
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138346
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/138346 | Memory device with improved writing features | Sep 20, 2018 | Issued |
Array
(
[id] => 14024113
[patent_doc_number] => 20190074050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-07
[patent_title] => METHOD FOR PROGRAMMING A ONE-TRANSISTOR DRAM MEMORY CELL AND MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/120858
[patent_app_country] => US
[patent_app_date] => 2018-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5651
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120858
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/120858 | Method for programming a one-transistor DRAM memory cell and memory device | Sep 3, 2018 | Issued |
Array
(
[id] => 15889071
[patent_doc_number] => 10650884
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Superconducting memory with josephson phase-based torque
[patent_app_type] => utility
[patent_app_number] => 16/120882
[patent_app_country] => US
[patent_app_date] => 2018-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 8687
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120882
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/120882 | Superconducting memory with josephson phase-based torque | Sep 3, 2018 | Issued |
Array
(
[id] => 14874791
[patent_doc_number] => 20190287637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => MAGNETIC MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/120636
[patent_app_country] => US
[patent_app_date] => 2018-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6458
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16120636
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/120636 | Magnetic memory device | Sep 3, 2018 | Issued |
Array
(
[id] => 14691117
[patent_doc_number] => 20190244674
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/114770
[patent_app_country] => US
[patent_app_date] => 2018-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13838
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114770
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/114770 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME | Aug 27, 2018 | Abandoned |
Array
(
[id] => 15231725
[patent_doc_number] => 10503585
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Memory system
[patent_app_type] => utility
[patent_app_number] => 16/115520
[patent_app_country] => US
[patent_app_date] => 2018-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 30
[patent_no_of_words] => 20289
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16115520
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/115520 | Memory system | Aug 27, 2018 | Issued |
Array
(
[id] => 14508931
[patent_doc_number] => 20190198120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-27
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/115516
[patent_app_country] => US
[patent_app_date] => 2018-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10109
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16115516
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/115516 | Memory system | Aug 27, 2018 | Issued |
Array
(
[id] => 15547171
[patent_doc_number] => 10573375
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-02-25
[patent_title] => Methods and circuitry for programming non-volatile resistive switches using varistors
[patent_app_type] => utility
[patent_app_number] => 16/114892
[patent_app_country] => US
[patent_app_date] => 2018-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 7922
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114892
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/114892 | Methods and circuitry for programming non-volatile resistive switches using varistors | Aug 27, 2018 | Issued |
Array
(
[id] => 14769451
[patent_doc_number] => 10396127
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Constructions comprising stacked memory arrays
[patent_app_type] => utility
[patent_app_number] => 16/103032
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6131
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103032
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/103032 | Constructions comprising stacked memory arrays | Aug 13, 2018 | Issued |
Array
(
[id] => 15502897
[patent_doc_number] => 20200051637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => METHOD FOR OPERATING MEMORY ARRAY
[patent_app_type] => utility
[patent_app_number] => 16/057864
[patent_app_country] => US
[patent_app_date] => 2018-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4030
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057864
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/057864 | METHOD FOR OPERATING MEMORY ARRAY | Aug 7, 2018 | Abandoned |
Array
(
[id] => 14078865
[patent_doc_number] => 20190088320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-21
[patent_title] => 2T1C Ferro-electric Random Access Memory Cell
[patent_app_type] => utility
[patent_app_number] => 16/056874
[patent_app_country] => US
[patent_app_date] => 2018-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7744
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056874
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/056874 | 2T1C ferro-electric random access memory cell | Aug 6, 2018 | Issued |