Search

Tri M. Hoang

Examiner (ID: 17092, Phone: (571)270-1515 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
731
Issued Applications
674
Pending Applications
0
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15502919 [patent_doc_number] => 20200051648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => NON-VOLATILE MEMORY WITH COUNTERMEASURES FOR SELECT GATE DISTURB DURING PROGRAM PRE-CHARGE [patent_app_type] => utility [patent_app_number] => 16/056838 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056838 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056838
Non-volatile memory with countermeasures for select gate disturb during program pre-charge Aug 6, 2018 Issued
Array ( [id] => 13995255 [patent_doc_number] => 20190066785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => MEMORY CELL, MEMORY CELL ARRAY, MEMORY DEVICE AND OPERATION METHOD OF MEMORY CELL ARRAY [patent_app_type] => utility [patent_app_number] => 16/057316 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057316
Memory cell, memory cell array, memory device and operation method of memory cell array Aug 6, 2018 Issued
Array ( [id] => 13613081 [patent_doc_number] => 20180358090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => APPARATUSES AND METHODS OF READING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/045523 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/045523
Apparatuses and methods of reading memory cells Jul 24, 2018 Issued
Array ( [id] => 16193913 [patent_doc_number] => 20200234762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => DIFFERENTIAL MEMRISTIVE CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/634148 [patent_app_country] => US [patent_app_date] => 2018-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16634148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/634148
Differential memristive circuit Jul 21, 2018 Issued
Array ( [id] => 14557737 [patent_doc_number] => 10347336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-09 [patent_title] => Method for obtaining optimal operating condition of resistive random access memory [patent_app_type] => utility [patent_app_number] => 16/040552 [patent_app_country] => US [patent_app_date] => 2018-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5538 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040552
Method for obtaining optimal operating condition of resistive random access memory Jul 19, 2018 Issued
Array ( [id] => 14675995 [patent_doc_number] => 20190237112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => INTEGRATED CIRCUIT DEVICES HAVING STROBE SIGNAL TRANSMITTERS WITH ENHANCED DRIVE CHARACTERISTICS [patent_app_type] => utility [patent_app_number] => 16/040702 [patent_app_country] => US [patent_app_date] => 2018-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040702
Integrated circuit devices having strobe signal transmitters with enhanced drive characteristics Jul 19, 2018 Issued
Array ( [id] => 15640819 [patent_doc_number] => 10593412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Using a status indicator in a memory sub-system to detect an event [patent_app_type] => utility [patent_app_number] => 16/040382 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040382
Using a status indicator in a memory sub-system to detect an event Jul 18, 2018 Issued
Array ( [id] => 13847457 [patent_doc_number] => 20190027213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => STATIC RANDOM ACCESS MEMORY INCLUDING ASSIST CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/038414 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038414
Static random access memory including assist circuit Jul 17, 2018 Issued
Array ( [id] => 14508929 [patent_doc_number] => 20190198119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/037588 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037588
Memory system and operation method thereof Jul 16, 2018 Issued
Array ( [id] => 14446471 [patent_doc_number] => 20190181109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => SEMICONDUCTOR MEMORY INCLUDING PADS ARRANGED IN PARALLEL [patent_app_type] => utility [patent_app_number] => 16/036198 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/036198
Semiconductor memory including pads arranged in parallel Jul 15, 2018 Issued
Array ( [id] => 14557669 [patent_doc_number] => 10347302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-09 [patent_title] => Memory layout for preventing reference layer from breaks [patent_app_type] => utility [patent_app_number] => 16/035868 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1866 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035868 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035868
Memory layout for preventing reference layer from breaks Jul 15, 2018 Issued
Array ( [id] => 14252077 [patent_doc_number] => 10276245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Semiconductor memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/035430 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12786 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035430
Semiconductor memory device and method of operating the same Jul 12, 2018 Issued
Array ( [id] => 13570787 [patent_doc_number] => 20180336941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => FULL BIAS SENSING IN A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/030590 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030590
Full bias sensing in a memory array Jul 8, 2018 Issued
Array ( [id] => 14888613 [patent_doc_number] => 10424353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Current-sensing circuit for memory and sensing method thereof [patent_app_type] => utility [patent_app_number] => 16/008042 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3866 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008042
Current-sensing circuit for memory and sensing method thereof Jun 13, 2018 Issued
Array ( [id] => 15138987 [patent_doc_number] => 10482975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Flash memory cell with dual erase modes for increased cell endurance [patent_app_type] => utility [patent_app_number] => 16/008234 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3333 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008234 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008234
Flash memory cell with dual erase modes for increased cell endurance Jun 13, 2018 Issued
Array ( [id] => 13486543 [patent_doc_number] => 20180294814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => DATA PROCESSING DEVICE AND CONTROL METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/004975 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004975 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004975
DATA PROCESSING DEVICE AND CONTROL METHOD THEREFOR Jun 10, 2018 Abandoned
Array ( [id] => 14063499 [patent_doc_number] => 10236050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Optimizing data approximation analysis using low power circuitry [patent_app_type] => utility [patent_app_number] => 16/001420 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7943 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001420 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001420
Optimizing data approximation analysis using low power circuitry Jun 5, 2018 Issued
Array ( [id] => 14011229 [patent_doc_number] => 10224089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Optimizing data approximation analysis using low bower circuitry [patent_app_type] => utility [patent_app_number] => 16/000207 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7969 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/000207
Optimizing data approximation analysis using low bower circuitry Jun 4, 2018 Issued
Array ( [id] => 14177437 [patent_doc_number] => 10262739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Devices including memory arrays, row decoder circuitries and column decoder circuitries [patent_app_type] => utility [patent_app_number] => 15/995626 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15995626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/995626
Devices including memory arrays, row decoder circuitries and column decoder circuitries May 31, 2018 Issued
Array ( [id] => 13419443 [patent_doc_number] => 20180261264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SHIFTING DATA IN SENSING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 15/978578 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978578 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978578
Shifting data in sensing circuitry May 13, 2018 Issued
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