Search

Tri M. Hoang

Examiner (ID: 8315, Phone: (571)270-1515 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
731
Issued Applications
674
Pending Applications
0
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11869282 [patent_doc_number] => 20170236567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SYSTEMS AND METHODS FOR INDIVIDUALLY CONFIGURING DYNAMIC RANDOM ACCESS MEMORIES SHARING A COMMON COMMAND ACCESS BUS' [patent_app_type] => utility [patent_app_number] => 15/142316 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9498 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15142316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/142316
Systems and methods for individually configuring dynamic random access memories sharing a common command access bus Apr 28, 2016 Issued
Array ( [id] => 11904090 [patent_doc_number] => 09773528 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Socket with branching point' [patent_app_type] => utility [patent_app_number] => 15/141650 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5832 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141650 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141650
Socket with branching point Apr 27, 2016 Issued
Array ( [id] => 11592634 [patent_doc_number] => 20170117046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/141812 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7180 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141812 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141812
Non-volatile semiconductor memory device Apr 27, 2016 Issued
Array ( [id] => 12005179 [patent_doc_number] => 20170309334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'METHODS FOR ENHANCED STATE RETENTION WITHIN A RESISTIVE CHANGE CELL' [patent_app_type] => utility [patent_app_number] => 15/136414 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 7916 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15136414 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/136414
Methods for enhanced state retention within a resistive change cell Apr 21, 2016 Issued
Array ( [id] => 11117871 [patent_doc_number] => 20160314845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'Method for determining an optimal voltage pulse for programming a flash memory cell' [patent_app_type] => utility [patent_app_number] => 15/132862 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6294 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132862 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132862
Method for determining an optimal voltage pulse for programming a flash memory cell Apr 18, 2016 Issued
Array ( [id] => 11564451 [patent_doc_number] => 09627043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => '9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write' [patent_app_type] => utility [patent_app_number] => 15/096563 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4313 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096563
9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write Apr 11, 2016 Issued
Array ( [id] => 11725027 [patent_doc_number] => 09697888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-04 [patent_title] => '9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write' [patent_app_type] => utility [patent_app_number] => 15/096434 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4393 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096434 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096434
9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write Apr 11, 2016 Issued
Array ( [id] => 11890725 [patent_doc_number] => 09761288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Memory circuit and stack type memory system including the same' [patent_app_type] => utility [patent_app_number] => 15/096578 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3955 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15096578 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/096578
Memory circuit and stack type memory system including the same Apr 11, 2016 Issued
Array ( [id] => 11615289 [patent_doc_number] => 09653150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Static random access memory (SRAM) bitcell and memory architecture without a write bitline' [patent_app_type] => utility [patent_app_number] => 15/090850 [patent_app_country] => US [patent_app_date] => 2016-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5166 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090850
Static random access memory (SRAM) bitcell and memory architecture without a write bitline Apr 4, 2016 Issued
Array ( [id] => 14153595 [patent_doc_number] => 10257191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Biometric identity verification [patent_app_type] => utility [patent_app_number] => 15/083855 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7776 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083855
Biometric identity verification Mar 28, 2016 Issued
Array ( [id] => 11333540 [patent_doc_number] => 09524789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-20 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 15/073555 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8382 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073555
Semiconductor memory device Mar 16, 2016 Issued
Array ( [id] => 10983989 [patent_doc_number] => 20160180933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHODS AND APPARATUSES HAVING A VOLTAGE GENERATOR WITH AN ADJUSTABLE VOLTAGE DROP FOR REPRESENTING A VOLTAGE DROP OF A MEMORY CELL AND/OR A CURRENT MIRROR CIRCUIT AND REPLICA CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/054984 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054984 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/054984
Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage drop of a memory cell and/or a current mirror circuit and replica circuit Feb 25, 2016 Issued
Array ( [id] => 11110641 [patent_doc_number] => 20160307611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'Memory Device with Internal Combination Logic' [patent_app_type] => utility [patent_app_number] => 15/052709 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5175 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052709
Memory device with internal combination logic Feb 23, 2016 Issued
Array ( [id] => 11043293 [patent_doc_number] => 20160240249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'RESISTANCE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 15/040921 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7995 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/040921
Resistance memory cell Feb 9, 2016 Issued
Array ( [id] => 10825879 [patent_doc_number] => 20160172047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/019256 [patent_app_country] => US [patent_app_date] => 2016-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15019256 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/019256
Semiconductor device and operating method thereof Feb 8, 2016 Issued
Array ( [id] => 14297937 [patent_doc_number] => 10289092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Digital motor controller stability analysis tool [patent_app_type] => utility [patent_app_number] => 14/995691 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2913 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995691 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995691
Digital motor controller stability analysis tool Jan 13, 2016 Issued
Array ( [id] => 10779805 [patent_doc_number] => 20160125961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'Semiconductor Device Having Hierarchically Structured Bit Lines' [patent_app_type] => utility [patent_app_number] => 14/992645 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8003 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992645 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/992645
Semiconductor device having hierarchically structured bit lines Jan 10, 2016 Issued
Array ( [id] => 11265708 [patent_doc_number] => 09490008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-08 [patent_title] => '9T, 8T, and 7T Bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write' [patent_app_type] => utility [patent_app_number] => 14/976065 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976065 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/976065
9T, 8T, and 7T Bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write Dec 20, 2015 Issued
Array ( [id] => 11918167 [patent_doc_number] => 09786358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => '6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write' [patent_app_type] => utility [patent_app_number] => 14/976723 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2415 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976723 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/976723
6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write Dec 20, 2015 Issued
Array ( [id] => 14734001 [patent_doc_number] => 10386396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Hybrid PLL for grid synchronization in distributed generation [patent_app_type] => utility [patent_app_number] => 14/875993 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5277 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875993 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/875993
Hybrid PLL for grid synchronization in distributed generation Oct 5, 2015 Issued
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