Search

Tri M. Hoang

Examiner (ID: 17092, Phone: (571)270-1515 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
731
Issued Applications
674
Pending Applications
0
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18120340 [patent_doc_number] => 11551738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Memory device and method for operating memory device [patent_app_type] => utility [patent_app_number] => 17/225116 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3684 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225116 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225116
Memory device and method for operating memory device Apr 7, 2021 Issued
Array ( [id] => 17485651 [patent_doc_number] => 20220093155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MEMORY SYSTEM AND CONTROLLING METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/201127 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201127
Memory system and controlling method of memory system Mar 14, 2021 Issued
Array ( [id] => 18155916 [patent_doc_number] => 11568905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Page buffer and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/200246 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 9178 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200246
Page buffer and memory device including the same Mar 11, 2021 Issued
Array ( [id] => 17508785 [patent_doc_number] => 20220101888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, PROCESSING SYSTEM INCLUDING THE SAME AND POWER CONTROL CIRCUIT FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/191499 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191499
Semiconductor memory device, processing system including the same and power control circuit for the same Mar 2, 2021 Issued
Array ( [id] => 17040385 [patent_doc_number] => 20210257021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => Pooled DRAM System Enabled by Monolithic In-Package Optical I/O [patent_app_type] => utility [patent_app_number] => 17/175678 [patent_app_country] => US [patent_app_date] => 2021-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175678 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175678
Pooled DRAM system enabled by monolithic in-package optical I/O Feb 13, 2021 Issued
Array ( [id] => 17152280 [patent_doc_number] => 11145367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Techniques for read operations [patent_app_type] => utility [patent_app_number] => 17/174117 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 23242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174117 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174117
Techniques for read operations Feb 10, 2021 Issued
Array ( [id] => 17516644 [patent_doc_number] => 11295804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Output circuit and chip [patent_app_type] => utility [patent_app_number] => 17/172319 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172319
Output circuit and chip Feb 9, 2021 Issued
Array ( [id] => 17795338 [patent_doc_number] => 20220254430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => RESET READ DISTURB MITIGATION [patent_app_type] => utility [patent_app_number] => 17/171838 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171838
Reset read disturb mitigation Feb 8, 2021 Issued
Array ( [id] => 17529683 [patent_doc_number] => 11302381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Sub word line driver [patent_app_type] => utility [patent_app_number] => 17/170743 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 22476 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170743
Sub word line driver Feb 7, 2021 Issued
Array ( [id] => 17752459 [patent_doc_number] => 20220230664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => REDUCED PIN STATUS REGISTER [patent_app_type] => utility [patent_app_number] => 17/155070 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155070
Reduced pin status register Jan 20, 2021 Issued
Array ( [id] => 17558916 [patent_doc_number] => 11315635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same [patent_app_type] => utility [patent_app_number] => 17/152696 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4873 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152696
Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same Jan 18, 2021 Issued
Array ( [id] => 16981190 [patent_doc_number] => 20210225427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/147658 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147658
Semiconductor device Jan 12, 2021 Issued
Array ( [id] => 17737730 [patent_doc_number] => 20220223192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/147480 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147480
Memory device Jan 12, 2021 Issued
Array ( [id] => 18088369 [patent_doc_number] => 11538508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Memory module multiple port buffer techniques [patent_app_type] => utility [patent_app_number] => 17/137975 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137975
Memory module multiple port buffer techniques Dec 29, 2020 Issued
Array ( [id] => 16781416 [patent_doc_number] => 20210118495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/137723 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137723
Semiconductor memory device and memory system Dec 29, 2020 Issued
Array ( [id] => 17455889 [patent_doc_number] => 11270755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-08 [patent_title] => Flash memory device and control method [patent_app_type] => utility [patent_app_number] => 17/132999 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2699 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132999 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132999
Flash memory device and control method Dec 22, 2020 Issued
Array ( [id] => 16752265 [patent_doc_number] => 20210104277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => VARIABLY RESISTIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/123830 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123830
Variably resistive memory device Dec 15, 2020 Issued
Array ( [id] => 17676364 [patent_doc_number] => 20220189531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => RECONFIGURABLE PROCESSING-IN-MEMORY LOGIC [patent_app_type] => utility [patent_app_number] => 17/123829 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123829
Reconfigurable processing-in-memory logic Dec 15, 2020 Issued
Array ( [id] => 17309976 [patent_doc_number] => 11211100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Recovery of memory from asynchronous power loss [patent_app_type] => utility [patent_app_number] => 17/122531 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122531
Recovery of memory from asynchronous power loss Dec 14, 2020 Issued
Array ( [id] => 16920160 [patent_doc_number] => 20210193252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => LINK EVALUATION FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/121314 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121314
Link evaluation for a memory device Dec 13, 2020 Issued
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