
Tri M. Hoang
Examiner (ID: 17092, Phone: (571)270-1515 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 731 |
| Issued Applications | 674 |
| Pending Applications | 0 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17195868
[patent_doc_number] => 11164633
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Memory device using comb-like routing structure for reduced metal line loading
[patent_app_type] => utility
[patent_app_number] => 17/112403
[patent_app_country] => US
[patent_app_date] => 2020-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8747
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112403
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/112403 | Memory device using comb-like routing structure for reduced metal line loading | Dec 3, 2020 | Issued |
Array
(
[id] => 17353222
[patent_doc_number] => 11227869
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-01-18
[patent_title] => Memory array structures for capacitive sense NAND memory
[patent_app_type] => utility
[patent_app_number] => 17/111746
[patent_app_country] => US
[patent_app_date] => 2020-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 59
[patent_no_of_words] => 22391
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111746
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/111746 | Memory array structures for capacitive sense NAND memory | Dec 3, 2020 | Issued |
Array
(
[id] => 17438769
[patent_doc_number] => 11264109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-01
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 17/111323
[patent_app_country] => US
[patent_app_date] => 2020-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8241
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111323
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/111323 | Memory device | Dec 2, 2020 | Issued |
Array
(
[id] => 17092691
[patent_doc_number] => 11120885
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Using a status indicator in a memory sub-system to detect an event
[patent_app_type] => utility
[patent_app_number] => 17/100582
[patent_app_country] => US
[patent_app_date] => 2020-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7529
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100582
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/100582 | Using a status indicator in a memory sub-system to detect an event | Nov 19, 2020 | Issued |
Array
(
[id] => 16723507
[patent_doc_number] => 20210090654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => TEMPERATURE COMPENSATION IN AN ANALOG MEMORY ARRAY BY CHANGING A THRESHOLD VOLTAGE OF A SELECTED MEMORY CELL IN THE ARRAY
[patent_app_type] => utility
[patent_app_number] => 17/095661
[patent_app_country] => US
[patent_app_date] => 2020-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11747
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -37
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095661
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/095661 | Temperature compensation in an analog memory array by changing a threshold voltage of a selected memory cell in the array | Nov 10, 2020 | Issued |
Array
(
[id] => 17493254
[patent_doc_number] => 11282564
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-03-22
[patent_title] => Selective wordline scans based on a data state metric
[patent_app_type] => utility
[patent_app_number] => 17/094970
[patent_app_country] => US
[patent_app_date] => 2020-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8073
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094970
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094970 | Selective wordline scans based on a data state metric | Nov 10, 2020 | Issued |
Array
(
[id] => 17941517
[patent_doc_number] => 11475976
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-18
[patent_title] => Latch circuit and semiconductor memory device including the same
[patent_app_type] => utility
[patent_app_number] => 17/094075
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6091
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094075
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094075 | Latch circuit and semiconductor memory device including the same | Nov 9, 2020 | Issued |
Array
(
[id] => 17395718
[patent_doc_number] => 11244741
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-02-08
[patent_title] => Selectable fuse sets, and related methods, devices, and systems
[patent_app_type] => utility
[patent_app_number] => 17/089002
[patent_app_country] => US
[patent_app_date] => 2020-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8333
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089002
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089002 | Selectable fuse sets, and related methods, devices, and systems | Nov 3, 2020 | Issued |
Array
(
[id] => 16631400
[patent_doc_number] => 20210050053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => Low Voltage Bit-Cell
[patent_app_type] => utility
[patent_app_number] => 17/087711
[patent_app_country] => US
[patent_app_date] => 2020-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7231
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087711
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/087711 | Low voltage bit-cell | Nov 2, 2020 | Issued |
Array
(
[id] => 17558920
[patent_doc_number] => 11315639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-26
[patent_title] => Memory device having vertical structure
[patent_app_type] => utility
[patent_app_number] => 17/087096
[patent_app_country] => US
[patent_app_date] => 2020-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 16648
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087096
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/087096 | Memory device having vertical structure | Nov 1, 2020 | Issued |
Array
(
[id] => 17566293
[patent_doc_number] => 20220130442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => MAGNETIC TUNNEL JUNCTION MEMORY DEVICES EMPLOYING RESONANT TUNNELING AND METHODS OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/081678
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13857
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081678
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081678 | Magnetic tunnel junction memory devices employing resonant tunneling and methods of manufacturing the same | Oct 26, 2020 | Issued |
Array
(
[id] => 17638329
[patent_doc_number] => 11349066
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-31
[patent_title] => Magnetic tunnel junction memory devices employing resonant tunneling and methods of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/081625
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 13846
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081625
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081625 | Magnetic tunnel junction memory devices employing resonant tunneling and methods of manufacturing the same | Oct 26, 2020 | Issued |
Array
(
[id] => 16795834
[patent_doc_number] => 20210125651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-29
[patent_title] => TOPOLOGICAL MATERIAL FOR TRAPPING CHARGE AND SWITCHING A FERROMAGNET
[patent_app_type] => utility
[patent_app_number] => 17/078764
[patent_app_country] => US
[patent_app_date] => 2020-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7836
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078764
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/078764 | Topological material for trapping charge and switching a ferromagnet | Oct 22, 2020 | Issued |
Array
(
[id] => 17971112
[patent_doc_number] => 11488659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-01
[patent_title] => Memory circuit and write method
[patent_app_type] => utility
[patent_app_number] => 17/069312
[patent_app_country] => US
[patent_app_date] => 2020-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 13591
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069312
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/069312 | Memory circuit and write method | Oct 12, 2020 | Issued |
Array
(
[id] => 16601280
[patent_doc_number] => 20210027811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-28
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/068903
[patent_app_country] => US
[patent_app_date] => 2020-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29413
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068903
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/068903 | Semiconductor memory device | Oct 12, 2020 | Issued |
Array
(
[id] => 16601308
[patent_doc_number] => 20210027839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-28
[patent_title] => SEQUENTIAL VOLTAGE RAMP-DOWN OF ACCESS LINES OF NON-VOLATILE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/067550
[patent_app_country] => US
[patent_app_date] => 2020-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067550
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/067550 | Sequential voltage ramp-down of access lines of non-volatile memory device | Oct 8, 2020 | Issued |
Array
(
[id] => 16850341
[patent_doc_number] => 20210151086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-20
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/061600
[patent_app_country] => US
[patent_app_date] => 2020-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7201
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061600
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/061600 | Memory device | Oct 1, 2020 | Issued |
Array
(
[id] => 17332210
[patent_doc_number] => 11222678
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-01-11
[patent_title] => MRAM cross-point memory with reversed MRAM element vertical orientation
[patent_app_type] => utility
[patent_app_number] => 17/061836
[patent_app_country] => US
[patent_app_date] => 2020-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 35
[patent_no_of_words] => 24961
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061836
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/061836 | MRAM cross-point memory with reversed MRAM element vertical orientation | Oct 1, 2020 | Issued |
Array
(
[id] => 16585859
[patent_doc_number] => 20210020261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-21
[patent_title] => APPARATUSES AND METHODS FOR SOFT POST-PACKAGE REPAIR
[patent_app_type] => utility
[patent_app_number] => 17/062264
[patent_app_country] => US
[patent_app_date] => 2020-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11957
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062264
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/062264 | Apparatuses and methods for soft post-package repair | Oct 1, 2020 | Issued |
Array
(
[id] => 17063368
[patent_doc_number] => 11107983
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-31
[patent_title] => Resistive random access memory array and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/060300
[patent_app_country] => US
[patent_app_date] => 2020-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6179
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060300
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/060300 | Resistive random access memory array and manufacturing method thereof | Sep 30, 2020 | Issued |