
Trisha U. Vu
Examiner (ID: 9280)
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2189, 2111, 2112 |
| Total Applications | 371 |
| Issued Applications | 278 |
| Pending Applications | 4 |
| Abandoned Applications | 90 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1161259
[patent_doc_number] => 06775727
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'System and method for controlling bus arbitration during cache memory burst cycles'
[patent_app_type] => B2
[patent_app_number] => 09/888278
[patent_app_country] => US
[patent_app_date] => 2001-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4853
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/775/06775727.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888278
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888278 | System and method for controlling bus arbitration during cache memory burst cycles | Jun 22, 2001 | Issued |
Array
(
[id] => 6335756
[patent_doc_number] => 20020199050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Method and apparatus to select configuration addresses for the peripherals in a computer system'
[patent_app_type] => new
[patent_app_number] => 09/887925
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2063
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20020199050.pdf
[firstpage_image] =>[orig_patent_app_number] => 09887925
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/887925 | Method and apparatus to select configuration addresses for the peripherals in a computer system | Jun 21, 2001 | Abandoned |
Array
(
[id] => 1203825
[patent_doc_number] => 06720801
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-13
[patent_title] => 'RS-232 bus data tap apparatus'
[patent_app_type] => B2
[patent_app_number] => 09/882987
[patent_app_country] => US
[patent_app_date] => 2001-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2215
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/720/06720801.pdf
[firstpage_image] =>[orig_patent_app_number] => 09882987
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882987 | RS-232 bus data tap apparatus | Jun 17, 2001 | Issued |
Array
(
[id] => 1149473
[patent_doc_number] => 06782442
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'CompactPCI hotswap automatic insertion/extraction test equipment'
[patent_app_type] => B2
[patent_app_number] => 09/882672
[patent_app_country] => US
[patent_app_date] => 2001-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2751
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/782/06782442.pdf
[firstpage_image] =>[orig_patent_app_number] => 09882672
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882672 | CompactPCI hotswap automatic insertion/extraction test equipment | Jun 14, 2001 | Issued |
Array
(
[id] => 962167
[patent_doc_number] => 06952746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-04
[patent_title] => 'Method and system for system performance optimization via heuristically optimized buses'
[patent_app_type] => utility
[patent_app_number] => 09/881922
[patent_app_country] => US
[patent_app_date] => 2001-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4445
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/952/06952746.pdf
[firstpage_image] =>[orig_patent_app_number] => 09881922
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/881922 | Method and system for system performance optimization via heuristically optimized buses | Jun 13, 2001 | Issued |
Array
(
[id] => 6988674
[patent_doc_number] => 20010037426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Interrupt handling via a proxy processor'
[patent_app_type] => new
[patent_app_number] => 09/837833
[patent_app_country] => US
[patent_app_date] => 2001-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6407
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20010037426.pdf
[firstpage_image] =>[orig_patent_app_number] => 09837833
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/837833 | Interrupt handling via a proxy processor | Apr 17, 2001 | Abandoned |
Array
(
[id] => 7321146
[patent_doc_number] => 20040225796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Expandable miniature accessory card for handheld computer'
[patent_app_type] => new
[patent_app_number] => 09/821522
[patent_app_country] => US
[patent_app_date] => 2001-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2144
[patent_no_of_claims] => 69
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0225/20040225796.pdf
[firstpage_image] =>[orig_patent_app_number] => 09821522
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/821522 | Expandable miniature accessory card for handheld computer | Mar 28, 2001 | Abandoned |
Array
(
[id] => 6892570
[patent_doc_number] => 20010018732
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-30
[patent_title] => 'Parallel processor and parallel processing method'
[patent_app_type] => new
[patent_app_number] => 09/760295
[patent_app_country] => US
[patent_app_date] => 2001-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 11973
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20010018732.pdf
[firstpage_image] =>[orig_patent_app_number] => 09760295
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/760295 | Parallel processor and parallel processing method | Jan 17, 2001 | Abandoned |
Array
(
[id] => 1165603
[patent_doc_number] => 06772268
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-03
[patent_title] => 'Centralized look up engine architecture and interface'
[patent_app_type] => B1
[patent_app_number] => 09/741852
[patent_app_country] => US
[patent_app_date] => 2000-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3965
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/772/06772268.pdf
[firstpage_image] =>[orig_patent_app_number] => 09741852
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/741852 | Centralized look up engine architecture and interface | Dec 21, 2000 | Issued |
Array
(
[id] => 6133929
[patent_doc_number] => 20020078284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Adaptive reader-writer lock'
[patent_app_type] => new
[patent_app_number] => 09/741679
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5440
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20020078284.pdf
[firstpage_image] =>[orig_patent_app_number] => 09741679
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/741679 | Adaptive reader-writer lock | Dec 18, 2000 | Issued |
Array
(
[id] => 1234208
[patent_doc_number] => 06697900
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-24
[patent_title] => 'Bus monitor and method of gathering bus phase information in real-time'
[patent_app_type] => B1
[patent_app_number] => 09/740907
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3442
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/697/06697900.pdf
[firstpage_image] =>[orig_patent_app_number] => 09740907
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/740907 | Bus monitor and method of gathering bus phase information in real-time | Dec 18, 2000 | Issued |
Array
(
[id] => 7623873
[patent_doc_number] => 06725304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-20
[patent_title] => 'Apparatus for connecting circuit modules'
[patent_app_type] => B2
[patent_app_number] => 09/740248
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2173
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 15
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/725/06725304.pdf
[firstpage_image] =>[orig_patent_app_number] => 09740248
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/740248 | Apparatus for connecting circuit modules | Dec 18, 2000 | Issued |
Array
(
[id] => 6565247
[patent_doc_number] => 20020112106
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-15
[patent_title] => 'Backplane physical layer controller with an internal bus reset'
[patent_app_type] => new
[patent_app_number] => 09/737922
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3867
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0112/20020112106.pdf
[firstpage_image] =>[orig_patent_app_number] => 09737922
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/737922 | Backplane physical layer controller with an internal bus reset | Dec 14, 2000 | Abandoned |
Array
(
[id] => 940395
[patent_doc_number] => 06973524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-06
[patent_title] => 'Interface for bus independent core'
[patent_app_type] => utility
[patent_app_number] => 09/736883
[patent_app_country] => US
[patent_app_date] => 2000-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2805
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/973/06973524.pdf
[firstpage_image] =>[orig_patent_app_number] => 09736883
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736883 | Interface for bus independent core | Dec 13, 2000 | Issued |
Array
(
[id] => 6133930
[patent_doc_number] => 20020078285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Reduction of interrupts in remote procedure calls'
[patent_app_type] => new
[patent_app_number] => 09/736582
[patent_app_country] => US
[patent_app_date] => 2000-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4693
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20020078285.pdf
[firstpage_image] =>[orig_patent_app_number] => 09736582
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736582 | Reduction of interrupts in remote procedure calls | Dec 13, 2000 | Issued |
Array
(
[id] => 1097295
[patent_doc_number] => 06826645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-30
[patent_title] => 'Apparatus and a method to provide higher bandwidth or processing power on a bus'
[patent_app_type] => B2
[patent_app_number] => 09/737648
[patent_app_country] => US
[patent_app_date] => 2000-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6425
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/826/06826645.pdf
[firstpage_image] =>[orig_patent_app_number] => 09737648
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/737648 | Apparatus and a method to provide higher bandwidth or processing power on a bus | Dec 12, 2000 | Issued |
Array
(
[id] => 6207471
[patent_doc_number] => 20020071431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Method and an apparatus for a re-configurable processor'
[patent_app_type] => new
[patent_app_number] => 09/738913
[patent_app_country] => US
[patent_app_date] => 2000-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6005
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 25
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20020071431.pdf
[firstpage_image] =>[orig_patent_app_number] => 09738913
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/738913 | Method and an apparatus for a re-configurable processor | Dec 12, 2000 | Issued |
Array
(
[id] => 6211524
[patent_doc_number] => 20020073264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Integrated co-processor configured as a PCI device'
[patent_app_type] => new
[patent_app_number] => 09/733766
[patent_app_country] => US
[patent_app_date] => 2000-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1222
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20020073264.pdf
[firstpage_image] =>[orig_patent_app_number] => 09733766
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/733766 | Integrated co-processor configured as a PCI device | Dec 7, 2000 | Abandoned |
Array
(
[id] => 6883288
[patent_doc_number] => 20010049760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-06
[patent_title] => 'Redundant bus controller for bus with several masters'
[patent_app_type] => new
[patent_app_number] => 09/726849
[patent_app_country] => US
[patent_app_date] => 2000-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2282
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20010049760.pdf
[firstpage_image] =>[orig_patent_app_number] => 09726849
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/726849 | Redundant bus controller for bus with several masters | Nov 29, 2000 | Abandoned |
Array
(
[id] => 739478
[patent_doc_number] => 07039742
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-05-02
[patent_title] => 'Handheld option pack identification scheme'
[patent_app_type] => utility
[patent_app_number] => 09/722890
[patent_app_country] => US
[patent_app_date] => 2000-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 9972
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/039/07039742.pdf
[firstpage_image] =>[orig_patent_app_number] => 09722890
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/722890 | Handheld option pack identification scheme | Nov 26, 2000 | Issued |