Search

Trisha U. Vu

Examiner (ID: 9280)

Most Active Art Unit
2111
Art Unit(s)
2181, 2189, 2111, 2112
Total Applications
371
Issued Applications
278
Pending Applications
4
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1271727 [patent_doc_number] => 06662254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'System architecture' [patent_app_type] => B1 [patent_app_number] => 09/599797 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5054 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662254.pdf [firstpage_image] =>[orig_patent_app_number] => 09599797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599797
System architecture Jun 21, 2000 Issued
Array ( [id] => 1364986 [patent_doc_number] => 06581119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Interrupt controller and a microcomputer incorporating this controller' [patent_app_type] => B1 [patent_app_number] => 09/598321 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6659 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581119.pdf [firstpage_image] =>[orig_patent_app_number] => 09598321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598321
Interrupt controller and a microcomputer incorporating this controller Jun 20, 2000 Issued
Array ( [id] => 6698141 [patent_doc_number] => 20030110335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => ' BUS TRANSACTION BETWEEN DEVICES IN A SYSTEM\n ' [patent_app_type] => voluntary [patent_app_number] => 09/593033 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3411 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110335.pdf [firstpage_image] =>[orig_patent_app_number] => 09593033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593033
BUS TRANSACTION BETWEEN DEVICES IN A SYSTEMn Jun 11, 2000 Abandoned
Array ( [id] => 1106165 [patent_doc_number] => 06816933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'Serial device daisy chaining method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/573001 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3836 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816933.pdf [firstpage_image] =>[orig_patent_app_number] => 09573001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573001
Serial device daisy chaining method and apparatus May 16, 2000 Issued
Array ( [id] => 1431838 [patent_doc_number] => 06516364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method for time coordination of the transmission of data on a bus' [patent_app_type] => B1 [patent_app_number] => 09/571229 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3820 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516364.pdf [firstpage_image] =>[orig_patent_app_number] => 09571229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571229
Method for time coordination of the transmission of data on a bus May 15, 2000 Issued
Array ( [id] => 1196910 [patent_doc_number] => 06732214 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Reducing power consumption and simultaneous switching in a bus interface' [patent_app_type] => B1 [patent_app_number] => 09/568739 [patent_app_country] => US [patent_app_date] => 2000-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2505 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732214.pdf [firstpage_image] =>[orig_patent_app_number] => 09568739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/568739
Reducing power consumption and simultaneous switching in a bus interface May 10, 2000 Issued
Array ( [id] => 1271738 [patent_doc_number] => 06662255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'System for housing CompactPCI adapters in a non-CompactPCI frame' [patent_app_type] => B1 [patent_app_number] => 09/561156 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1533 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662255.pdf [firstpage_image] =>[orig_patent_app_number] => 09561156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561156
System for housing CompactPCI adapters in a non-CompactPCI frame Apr 27, 2000 Issued
Array ( [id] => 653518 [patent_doc_number] => 07114020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-26 [patent_title] => 'Software mechanism for unique identification of SCSI device' [patent_app_type] => utility [patent_app_number] => 09/561444 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6610 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/114/07114020.pdf [firstpage_image] =>[orig_patent_app_number] => 09561444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561444
Software mechanism for unique identification of SCSI device Apr 27, 2000 Issued
Array ( [id] => 1308514 [patent_doc_number] => 06629175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Efficient adapter context switching' [patent_app_type] => B1 [patent_app_number] => 09/550182 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3358 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629175.pdf [firstpage_image] =>[orig_patent_app_number] => 09550182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/550182
Efficient adapter context switching Apr 13, 2000 Issued
Array ( [id] => 1178813 [patent_doc_number] => 06757763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Universal serial bus interfacing using FIFO buffers' [patent_app_type] => B1 [patent_app_number] => 09/545393 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 5720 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757763.pdf [firstpage_image] =>[orig_patent_app_number] => 09545393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545393
Universal serial bus interfacing using FIFO buffers Apr 6, 2000 Issued
Array ( [id] => 1229021 [patent_doc_number] => 06701398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Global bus synchronous transaction acknowledge with nonresponse detection' [patent_app_type] => B1 [patent_app_number] => 09/543806 [patent_app_country] => US [patent_app_date] => 2000-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6196 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701398.pdf [firstpage_image] =>[orig_patent_app_number] => 09543806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543806
Global bus synchronous transaction acknowledge with nonresponse detection Apr 5, 2000 Issued
Array ( [id] => 1250229 [patent_doc_number] => 06675253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Dynamic routing of data across multiple data paths from a source controller to a destination controller' [patent_app_type] => B1 [patent_app_number] => 09/542309 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675253.pdf [firstpage_image] =>[orig_patent_app_number] => 09542309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542309
Dynamic routing of data across multiple data paths from a source controller to a destination controller Apr 3, 2000 Issued
Array ( [id] => 1365140 [patent_doc_number] => 06581130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Dynamic remapping of address registers for address translation between multiple busses' [patent_app_type] => B1 [patent_app_number] => 09/542420 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6666 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581130.pdf [firstpage_image] =>[orig_patent_app_number] => 09542420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542420
Dynamic remapping of address registers for address translation between multiple busses Apr 3, 2000 Issued
Array ( [id] => 1429704 [patent_doc_number] => 06510483 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports' [patent_app_type] => B1 [patent_app_number] => 09/531365 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4310 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510483.pdf [firstpage_image] =>[orig_patent_app_number] => 09531365 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531365
Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports Mar 20, 2000 Issued
Array ( [id] => 1339053 [patent_doc_number] => 06601125 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Minimizing signal stub length for high speed busses' [patent_app_type] => B1 [patent_app_number] => 09/528757 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1636 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601125.pdf [firstpage_image] =>[orig_patent_app_number] => 09528757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/528757
Minimizing signal stub length for high speed busses Mar 16, 2000 Issued
Array ( [id] => 7630017 [patent_doc_number] => 06636922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Methods and apparatus for implementing a host side advanced serial protocol' [patent_app_type] => B1 [patent_app_number] => 09/526293 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 56 [patent_no_of_words] => 28916 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636922.pdf [firstpage_image] =>[orig_patent_app_number] => 09526293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/526293
Methods and apparatus for implementing a host side advanced serial protocol Mar 14, 2000 Issued
Array ( [id] => 1329026 [patent_doc_number] => 06606677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'High speed interrupt controller' [patent_app_type] => B1 [patent_app_number] => 09/520876 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7009 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606677.pdf [firstpage_image] =>[orig_patent_app_number] => 09520876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520876
High speed interrupt controller Mar 6, 2000 Issued
Array ( [id] => 7630023 [patent_doc_number] => 06636916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Assigning PCI device interrupts in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/503749 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3755 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636916.pdf [firstpage_image] =>[orig_patent_app_number] => 09503749 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503749
Assigning PCI device interrupts in a computer system Feb 13, 2000 Issued
Array ( [id] => 6670411 [patent_doc_number] => 20030115396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Reconfigurable ieee 1149.1 bus interface' [patent_app_type] => new [patent_app_number] => 09/501477 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2932 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20030115396.pdf [firstpage_image] =>[orig_patent_app_number] => 09501477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501477
Reconfigurable IEEE 1149.1 bus interface Feb 8, 2000 Issued
Array ( [id] => 1200893 [patent_doc_number] => 06728808 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Mechanism for optimizing transaction retries within a system utilizing a PCI bus architecture' [patent_app_type] => B1 [patent_app_number] => 09/499504 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9687 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728808.pdf [firstpage_image] =>[orig_patent_app_number] => 09499504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499504
Mechanism for optimizing transaction retries within a system utilizing a PCI bus architecture Feb 6, 2000 Issued
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