Search

Trong Q Phan

Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2827, 2511, 2504, 2824, 2825, 2899, 2818
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10003876 [patent_doc_number] => 09047974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Erased state reading' [patent_app_type] => utility [patent_app_number] => 13/783068 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7065 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783068 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783068
Erased state reading Feb 28, 2013 Issued
Array ( [id] => 9014894 [patent_doc_number] => 20130229858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'Fault Tolerant Static Random-Access Memory' [patent_app_type] => utility [patent_app_number] => 13/782114 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13782114 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/782114
Fault Tolerant Static Random-Access Memory Feb 28, 2013 Abandoned
Array ( [id] => 9014897 [patent_doc_number] => 20130229861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'DRIVING METHOD OF SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/780791 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 18878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13780791 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/780791
Driving method of semiconductor storage device and semiconductor storage device Feb 27, 2013 Issued
Array ( [id] => 9377274 [patent_doc_number] => 08681544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Method of operating semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/779836 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8826 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13779836 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/779836
Method of operating semiconductor memory device Feb 27, 2013 Issued
Array ( [id] => 9684324 [patent_doc_number] => 20140241087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SENSE AMPLIFIER' [patent_app_type] => utility [patent_app_number] => 13/780772 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13780772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/780772
Sense amplifier Feb 27, 2013 Issued
Array ( [id] => 9014899 [patent_doc_number] => 20130229863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'HIGH-EFFICIENCY DRIVING STAGE FOR PHASE CHANGE NON-VOLATILE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/771663 [patent_app_country] => US [patent_app_date] => 2013-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6620 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13771663 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/771663
High-efficiency driving stage for phase change non-volatile memory devices Feb 19, 2013 Issued
Array ( [id] => 9669476 [patent_doc_number] => 20140233339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS' [patent_app_type] => utility [patent_app_number] => 13/769403 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4544 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769403 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769403
APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS Feb 17, 2013 Abandoned
Array ( [id] => 9002010 [patent_doc_number] => 20130223135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/766971 [patent_app_country] => US [patent_app_date] => 2013-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 23215 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766971 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766971
Semiconductor device Feb 13, 2013 Issued
Array ( [id] => 9877158 [patent_doc_number] => 08964439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Semiconductor device having hierarchical bit line structure' [patent_app_type] => utility [patent_app_number] => 13/767481 [patent_app_country] => US [patent_app_date] => 2013-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13767481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/767481
Semiconductor device having hierarchical bit line structure Feb 13, 2013 Issued
Array ( [id] => 9890317 [patent_doc_number] => 08976584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Flash memory device and method of programming the same' [patent_app_type] => utility [patent_app_number] => 13/767535 [patent_app_country] => US [patent_app_date] => 2013-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13767535 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/767535
Flash memory device and method of programming the same Feb 13, 2013 Issued
Array ( [id] => 9567688 [patent_doc_number] => 20140185401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SENSING CIRCUIT, MEMORY DEVICE AND DATA DETECTING METHOD' [patent_app_type] => utility [patent_app_number] => 13/765513 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765513
Sensing circuit, memory device and data detecting method Feb 11, 2013 Issued
Array ( [id] => 10232117 [patent_doc_number] => 20150117111 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2015-04-30 [patent_title] => 'METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/758379 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3844 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758379 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758379
Methods for programming a memory device and memory devices Feb 3, 2013 Issued
Array ( [id] => 10232117 [patent_doc_number] => 20150117111 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2015-04-30 [patent_title] => 'METHODS FOR PROGRAMMING A MEMORY DEVICE AND MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/758379 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3844 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758379 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758379
Methods for programming a memory device and memory devices Feb 3, 2013 Issued
Array ( [id] => 9470732 [patent_doc_number] => 08724375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'SRAM cell having an N-well bias' [patent_app_type] => utility [patent_app_number] => 13/758692 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 18770 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758692 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758692
SRAM cell having an N-well bias Feb 3, 2013 Issued
Array ( [id] => 9292971 [patent_doc_number] => 20140036605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'RESISTIVE SWITCHING FOR NON VOLATILE MEMORY DEVICE USING AN INTEGRATED BREAKDOWN ELEMENT' [patent_app_type] => utility [patent_app_number] => 13/735814 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5734 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735814
Resistive switching for non volatile memory device using an integrated breakdown element Jan 6, 2013 Issued
Array ( [id] => 9525728 [patent_doc_number] => 08750012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-10 [patent_title] => 'Racetrack memory with low-power write' [patent_app_type] => utility [patent_app_number] => 13/734642 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3900 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734642 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734642
Racetrack memory with low-power write Jan 3, 2013 Issued
Array ( [id] => 9877212 [patent_doc_number] => 08964493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Defective memory column replacement with load isolation' [patent_app_type] => utility [patent_app_number] => 13/733948 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733948 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733948
Defective memory column replacement with load isolation Jan 3, 2013 Issued
Array ( [id] => 10852608 [patent_doc_number] => 08879303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Pre-charge tracking of global read lines in high speed SRAM' [patent_app_type] => utility [patent_app_number] => 13/733578 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4706 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733578
Pre-charge tracking of global read lines in high speed SRAM Jan 2, 2013 Issued
Array ( [id] => 9014891 [patent_doc_number] => 20130229855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'RESISTIVE MEMORY DEVICE HAVING DEFINED OR VARIABLE ERASE UNIT SIZE' [patent_app_type] => utility [patent_app_number] => 13/733384 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733384 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733384
Resistive memory device having defined or variable erase unit size Jan 2, 2013 Issued
Array ( [id] => 8949103 [patent_doc_number] => 20130194883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'OPERATING METHOD AND DATA READ METHOD IN NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/733328 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733328
Operating method and data read method in nonvolatile memory device Jan 2, 2013 Issued
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