Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4073172 [patent_doc_number] => 05896319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Current control circuit and non-volatile semiconductor memory device having the same' [patent_app_type] => 1 [patent_app_number] => 8/976575 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4517 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896319.pdf [firstpage_image] =>[orig_patent_app_number] => 976575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976575
Current control circuit and non-volatile semiconductor memory device having the same Nov 23, 1997 Issued
Array ( [id] => 4077591 [patent_doc_number] => 05867429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates' [patent_app_type] => 1 [patent_app_number] => 8/974276 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5013 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867429.pdf [firstpage_image] =>[orig_patent_app_number] => 974276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974276
High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates Nov 18, 1997 Issued
Array ( [id] => 4093656 [patent_doc_number] => 06055203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Row decoder' [patent_app_type] => 1 [patent_app_number] => 8/974007 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4068 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055203.pdf [firstpage_image] =>[orig_patent_app_number] => 974007 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974007
Row decoder Nov 18, 1997 Issued
Array ( [id] => 3957253 [patent_doc_number] => 05982675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Cache memory and microprocessor having the same' [patent_app_type] => 1 [patent_app_number] => 8/972731 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6053 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982675.pdf [firstpage_image] =>[orig_patent_app_number] => 972731 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972731
Cache memory and microprocessor having the same Nov 17, 1997 Issued
Array ( [id] => 4170426 [patent_doc_number] => 06157582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Dynamic pull-up suppressor for column redundancy write schemes with redundant data lines' [patent_app_type] => 1 [patent_app_number] => 8/971627 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7627 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157582.pdf [firstpage_image] =>[orig_patent_app_number] => 971627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971627
Dynamic pull-up suppressor for column redundancy write schemes with redundant data lines Nov 16, 1997 Issued
Array ( [id] => 3963623 [patent_doc_number] => 05978251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Plate line driver circuit for a 1T/1C ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 8/970522 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 53 [patent_no_of_words] => 19571 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978251.pdf [firstpage_image] =>[orig_patent_app_number] => 970522 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970522
Plate line driver circuit for a 1T/1C ferroelectric memory Nov 13, 1997 Issued
Array ( [id] => 3994066 [patent_doc_number] => 05862097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/967575 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 14973 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862097.pdf [firstpage_image] =>[orig_patent_app_number] => 967575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967575
Semiconductor memory device Nov 9, 1997 Issued
Array ( [id] => 4067204 [patent_doc_number] => 05864499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Non-volatile data storage unit and method of controlling same' [patent_app_type] => 1 [patent_app_number] => 8/958487 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3990 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864499.pdf [firstpage_image] =>[orig_patent_app_number] => 958487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958487
Non-volatile data storage unit and method of controlling same Oct 23, 1997 Issued
Array ( [id] => 4230572 [patent_doc_number] => 06040999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/954174 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 16025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040999.pdf [firstpage_image] =>[orig_patent_app_number] => 954174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954174
Semiconductor memory device Oct 19, 1997 Issued
Array ( [id] => 3825055 [patent_doc_number] => 05812468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Programmable device for redundant element cancel in a memory' [patent_app_type] => 1 [patent_app_number] => 8/950012 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4249 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812468.pdf [firstpage_image] =>[orig_patent_app_number] => 950012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950012
Programmable device for redundant element cancel in a memory Oct 13, 1997 Issued
Array ( [id] => 3853714 [patent_doc_number] => 05848009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Integrated circuit memory devices that map nondefective memory cell blocks into continuous addresses' [patent_app_type] => 1 [patent_app_number] => 8/946471 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6501 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848009.pdf [firstpage_image] =>[orig_patent_app_number] => 946471 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946471
Integrated circuit memory devices that map nondefective memory cell blocks into continuous addresses Oct 6, 1997 Issued
Array ( [id] => 4077854 [patent_doc_number] => 05867445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Local word line decoder for memory with 2 MOS devices' [patent_app_type] => 1 [patent_app_number] => 8/944571 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1705 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867445.pdf [firstpage_image] =>[orig_patent_app_number] => 944571 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944571
Local word line decoder for memory with 2 MOS devices Oct 5, 1997 Issued
Array ( [id] => 3993686 [patent_doc_number] => 05862074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Integrated circuit memory devices having reconfigurable nonvolatile multi-bit memory cells therein and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 8/944876 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7388 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862074.pdf [firstpage_image] =>[orig_patent_app_number] => 944876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944876
Integrated circuit memory devices having reconfigurable nonvolatile multi-bit memory cells therein and methods of operating same Oct 5, 1997 Issued
Array ( [id] => 4073523 [patent_doc_number] => 05896344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Local word line decoder for memory with 2 1/2 MOS devices' [patent_app_type] => 1 [patent_app_number] => 8/944771 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1774 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896344.pdf [firstpage_image] =>[orig_patent_app_number] => 944771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/944771
Local word line decoder for memory with 2 1/2 MOS devices Oct 5, 1997 Issued
Array ( [id] => 4086049 [patent_doc_number] => 05966315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines' [patent_app_type] => 1 [patent_app_number] => 8/942275 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966315.pdf [firstpage_image] =>[orig_patent_app_number] => 942275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942275
Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines Sep 29, 1997 Issued
Array ( [id] => 4027132 [patent_doc_number] => 05880997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Bubbleback for FIFOS' [patent_app_type] => 1 [patent_app_number] => 8/939463 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3323 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880997.pdf [firstpage_image] =>[orig_patent_app_number] => 939463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939463
Bubbleback for FIFOS Sep 28, 1997 Issued
Array ( [id] => 3939928 [patent_doc_number] => 05877994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Space-efficient MDQ switch placement' [patent_app_type] => 1 [patent_app_number] => 8/938073 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4321 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877994.pdf [firstpage_image] =>[orig_patent_app_number] => 938073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938073
Space-efficient MDQ switch placement Sep 25, 1997 Issued
Array ( [id] => 3821335 [patent_doc_number] => 05831912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Semiconductor memory having space-efficient layout' [patent_app_type] => 1 [patent_app_number] => 8/938074 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4783 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831912.pdf [firstpage_image] =>[orig_patent_app_number] => 938074 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938074
Semiconductor memory having space-efficient layout Sep 25, 1997 Issued
Array ( [id] => 3980618 [patent_doc_number] => 05886930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Bit interleaving in a memory which uses multi-bit DRAMs' [patent_app_type] => 1 [patent_app_number] => 8/936672 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5584 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886930.pdf [firstpage_image] =>[orig_patent_app_number] => 936672 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936672
Bit interleaving in a memory which uses multi-bit DRAMs Sep 23, 1997 Issued
Array ( [id] => 3797943 [patent_doc_number] => 05822244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method and apparatus for suspending a program/erase operation in a flash memory' [patent_app_type] => 1 [patent_app_number] => 8/936373 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3444 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822244.pdf [firstpage_image] =>[orig_patent_app_number] => 936373 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936373
Method and apparatus for suspending a program/erase operation in a flash memory Sep 23, 1997 Issued
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