Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4131202 [patent_doc_number] => 06072724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Semiconductor integrated circuit for generating plurality of different reference levels' [patent_app_type] => 1 [patent_app_number] => 8/902275 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3857 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072724.pdf [firstpage_image] =>[orig_patent_app_number] => 902275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902275
Semiconductor integrated circuit for generating plurality of different reference levels Jul 28, 1997 Issued
Array ( [id] => 4005247 [patent_doc_number] => 05892729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Power savings for memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/900773 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3339 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892729.pdf [firstpage_image] =>[orig_patent_app_number] => 900773 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900773
Power savings for memory arrays Jul 24, 1997 Issued
Array ( [id] => 3888852 [patent_doc_number] => 05764584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Multi-bank synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/900650 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 56 [patent_no_of_words] => 25834 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764584.pdf [firstpage_image] =>[orig_patent_app_number] => 900650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900650
Multi-bank synchronous semiconductor memory device Jul 24, 1997 Issued
Array ( [id] => 3774921 [patent_doc_number] => 05844845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Data read circuit for use in semiconductor storage apparatus of CMOS memory' [patent_app_type] => 1 [patent_app_number] => 8/899773 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 18966 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844845.pdf [firstpage_image] =>[orig_patent_app_number] => 899773 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899773
Data read circuit for use in semiconductor storage apparatus of CMOS memory Jul 23, 1997 Issued
Array ( [id] => 3963824 [patent_doc_number] => 05978263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Negative voltage switch architecture for a nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 8/895613 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5228 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978263.pdf [firstpage_image] =>[orig_patent_app_number] => 895613 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895613
Negative voltage switch architecture for a nonvolatile memory Jul 17, 1997 Issued
Array ( [id] => 3937519 [patent_doc_number] => 05946265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Continuous burst EDO memory device' [patent_app_type] => 1 [patent_app_number] => 8/891557 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5465 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946265.pdf [firstpage_image] =>[orig_patent_app_number] => 891557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891557
Continuous burst EDO memory device Jul 10, 1997 Issued
Array ( [id] => 3845429 [patent_doc_number] => 05815432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Single-ended read, dual-ended write SCRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/891173 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3994 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815432.pdf [firstpage_image] =>[orig_patent_app_number] => 891173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891173
Single-ended read, dual-ended write SCRAM cell Jul 9, 1997 Issued
Array ( [id] => 3900707 [patent_doc_number] => 05777925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Semiconductor non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 8/888073 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5041 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777925.pdf [firstpage_image] =>[orig_patent_app_number] => 888073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888073
Semiconductor non-volatile memory device Jul 2, 1997 Issued
Array ( [id] => 4045580 [patent_doc_number] => 05856942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Flash memory array and decoding architecture' [patent_app_type] => 1 [patent_app_number] => 8/884926 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 11928 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 425 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856942.pdf [firstpage_image] =>[orig_patent_app_number] => 884926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884926
Flash memory array and decoding architecture Jun 29, 1997 Issued
Array ( [id] => 3825245 [patent_doc_number] => 05812485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Synchronous graphic RAM having block write control function' [patent_app_type] => 1 [patent_app_number] => 8/883375 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3534 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812485.pdf [firstpage_image] =>[orig_patent_app_number] => 883375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883375
Synchronous graphic RAM having block write control function Jun 25, 1997 Issued
Array ( [id] => 3798181 [patent_doc_number] => 05822262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Apparatus and method for a dynamic random access memory data sensing architecture' [patent_app_type] => 1 [patent_app_number] => 8/882472 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2513 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822262.pdf [firstpage_image] =>[orig_patent_app_number] => 882472 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882472
Apparatus and method for a dynamic random access memory data sensing architecture Jun 24, 1997 Issued
Array ( [id] => 3839322 [patent_doc_number] => 05815031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'High density dynamic bus routing scheme' [patent_app_type] => 1 [patent_app_number] => 8/878682 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2748 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815031.pdf [firstpage_image] =>[orig_patent_app_number] => 878682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878682
High density dynamic bus routing scheme Jun 18, 1997 Issued
Array ( [id] => 3889695 [patent_doc_number] => 05825711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method and system for storing and processing multiple memory addresses' [patent_app_type] => 1 [patent_app_number] => 8/874973 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4965 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825711.pdf [firstpage_image] =>[orig_patent_app_number] => 874973 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874973
Method and system for storing and processing multiple memory addresses Jun 12, 1997 Issued
Array ( [id] => 4061099 [patent_doc_number] => 05870334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/873015 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 10154 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870334.pdf [firstpage_image] =>[orig_patent_app_number] => 873015 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873015
Nonvolatile semiconductor memory device Jun 10, 1997 Issued
Array ( [id] => 4038436 [patent_doc_number] => 05903492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Semiconductor memory device and various systems mounting them' [patent_app_type] => 1 [patent_app_number] => 8/872874 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 155 [patent_figures_cnt] => 260 [patent_no_of_words] => 47800 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903492.pdf [firstpage_image] =>[orig_patent_app_number] => 872874 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872874
Semiconductor memory device and various systems mounting them Jun 9, 1997 Issued
Array ( [id] => 3900692 [patent_doc_number] => 05777924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Flash memory array and decoding architecture' [patent_app_type] => 1 [patent_app_number] => 8/872475 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8692 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777924.pdf [firstpage_image] =>[orig_patent_app_number] => 872475 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872475
Flash memory array and decoding architecture Jun 4, 1997 Issued
Array ( [id] => 3998791 [patent_doc_number] => 05959935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Synchronization signal generation circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/865748 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959935.pdf [firstpage_image] =>[orig_patent_app_number] => 865748 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865748
Synchronization signal generation circuit and method May 29, 1997 Issued
Array ( [id] => 4369397 [patent_doc_number] => 06169703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method for controlling high speed digital electronic memory' [patent_app_type] => 1 [patent_app_number] => 8/861274 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3477 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169703.pdf [firstpage_image] =>[orig_patent_app_number] => 861274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861274
Method for controlling high speed digital electronic memory May 20, 1997 Issued
Array ( [id] => 4038631 [patent_doc_number] => 05903505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions' [patent_app_type] => 1 [patent_app_number] => 8/858271 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4695 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903505.pdf [firstpage_image] =>[orig_patent_app_number] => 858271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858271
Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions May 18, 1997 Issued
Array ( [id] => 3802631 [patent_doc_number] => 05841717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Semiconductor memory device facilitating use of a high frequency clock signal' [patent_app_type] => 1 [patent_app_number] => 8/857173 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 32 [patent_no_of_words] => 6997 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841717.pdf [firstpage_image] =>[orig_patent_app_number] => 857173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857173
Semiconductor memory device facilitating use of a high frequency clock signal May 14, 1997 Issued
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