Trong Q. Phan

Array ( [id] => 4027335 [patent_doc_number] => 05881010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation' [patent_app_type] => 1 [patent_app_number] => 8/856972 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3673 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881010.pdf [firstpage_image] =>[orig_patent_app_number] => 856972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036972 [patent_doc_number] => 05883830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'CMOS imaging device with integrated flash memory image correction circuitry' [patent_app_type] => 1 [patent_app_number] => 8/855658 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4186 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883830.pdf [firstpage_image] =>[orig_patent_app_number] => 855658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3752057 [patent_doc_number] => 05787037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Non-volatile memory device which supplies erasable voltage to a flash memory cell' [patent_app_type] => 1 [patent_app_number] => 8/853675 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10134 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787037.pdf [firstpage_image] =>[orig_patent_app_number] => 853675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3905235 [patent_doc_number] => 05835429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Data retention weak write circuit and method of using same' [patent_app_type] => 1 [patent_app_number] => 8/854076 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3605 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835429.pdf [firstpage_image] =>[orig_patent_app_number] => 854076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3826075 [patent_doc_number] => 05771189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'DRAM cell and method of reading data from DRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/852072 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5518 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771189.pdf [firstpage_image] =>[orig_patent_app_number] => 852072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3821541 [patent_doc_number] => 05831927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Memory device and method for reading data therefrom' [patent_app_type] => 1 [patent_app_number] => 8/848340 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7979 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831927.pdf [firstpage_image] =>[orig_patent_app_number] => 848340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892353 [patent_doc_number] => 05805520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Integrated circuit address reconfigurability' [patent_app_type] => 1 [patent_app_number] => 8/842973 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2451 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805520.pdf [firstpage_image] =>[orig_patent_app_number] => 842973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873410 [patent_doc_number] => 05796666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Method and apparatus for quickly restoring digit I/O lines' [patent_app_type] => 1 [patent_app_number] => 8/831609 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2744 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796666.pdf [firstpage_image] =>[orig_patent_app_number] => 831609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3821568 [patent_doc_number] => 05831929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Memory device with staggered data paths' [patent_app_type] => 1 [patent_app_number] => 8/833376 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7095 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831929.pdf [firstpage_image] =>[orig_patent_app_number] => 833376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3948648 [patent_doc_number] => 05872737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Semiconductor integrated circuit device in which influence of power supply noise on internal circuitry during operation of input/output buffer is prevented' [patent_app_type] => 1 [patent_app_number] => 8/833171 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 39 [patent_no_of_words] => 17800 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872737.pdf [firstpage_image] =>[orig_patent_app_number] => 833171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892527 [patent_doc_number] => 05748545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Memory device with on-chip manufacturing and memory cell defect detection capability' [patent_app_type] => 1 [patent_app_number] => 8/834775 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11528 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748545.pdf [firstpage_image] =>[orig_patent_app_number] => 834775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155029 [patent_doc_number] => 06031757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Write protected, non-volatile memory device with user programmable sector lock capability' [patent_app_type] => 1 [patent_app_number] => 8/825879 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6684 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031757.pdf [firstpage_image] =>[orig_patent_app_number] => 825879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845353 [patent_doc_number] => 05815427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Modular memory circuit and method for forming same' [patent_app_type] => 1 [patent_app_number] => 8/825871 [patent_app_country] => US [patent_app_date] => 1997-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3850 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815427.pdf [firstpage_image] =>[orig_patent_app_number] => 825871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3809349 [patent_doc_number] => 05828610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Low power memory including selective precharge circuit' [patent_app_type] => 1 [patent_app_number] => 8/828571 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 6480 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828610.pdf [firstpage_image] =>[orig_patent_app_number] => 828571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3891742 [patent_doc_number] => 05798966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Flash memory VDS compensation techiques to reduce programming variability' [patent_app_type] => 1 [patent_app_number] => 8/828873 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798966.pdf [firstpage_image] =>[orig_patent_app_number] => 828873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050741 [patent_doc_number] => 05912592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Piezoelectric oscillator' [patent_app_type] => 1 [patent_app_number] => 8/765062 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 13800 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912592.pdf [firstpage_image] =>[orig_patent_app_number] => 765062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3797956 [patent_doc_number] => 05822245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Dual buffer flash memory architecture with multiple operating modes' [patent_app_type] => 1 [patent_app_number] => 8/824175 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 6556 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822245.pdf [firstpage_image] =>[orig_patent_app_number] => 824175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3756639 [patent_doc_number] => 05801987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Automatic transition charge pump for nonvolatile memories' [patent_app_type] => 1 [patent_app_number] => 8/818273 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3874 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801987.pdf [firstpage_image] =>[orig_patent_app_number] => 818273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3792339 [patent_doc_number] => 05818777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Circuit for implementing and method for initiating a self-refresh mode' [patent_app_type] => 1 [patent_app_number] => 8/812573 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3941 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818777.pdf [firstpage_image] =>[orig_patent_app_number] => 812573 [rel_patent_id] =>[rel_patent_doc_number] =>)