Trong Q. Phan

Array ( [id] => 3750641 [patent_doc_number] => 05801594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Quartz oscillator device and its adjusting method' [patent_app_type] => 1 [patent_app_number] => 8/750827 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801594.pdf [firstpage_image] =>[orig_patent_app_number] => 750827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845506 [patent_doc_number] => 05815437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Data input/output managing device, particularly for a non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/813171 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5120 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815437.pdf [firstpage_image] =>[orig_patent_app_number] => 813171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6139655 [patent_doc_number] => 20020001216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME' [patent_app_type] => new [patent_app_number] => 08/806674 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9181 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001216.pdf [firstpage_image] =>[orig_patent_app_number] => 08806674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3804412 [patent_doc_number] => 05726931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'DRAM with open digit lines and array edge reference sensing' [patent_app_type] => 1 [patent_app_number] => 8/804182 [patent_app_country] => US [patent_app_date] => 1997-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3216 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726931.pdf [firstpage_image] =>[orig_patent_app_number] => 804182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3783986 [patent_doc_number] => 05774408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'DRAM architecture with combined sense amplifier pitch' [patent_app_type] => 1 [patent_app_number] => 8/790375 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4657 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774408.pdf [firstpage_image] =>[orig_patent_app_number] => 790375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3868164 [patent_doc_number] => 05796311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Phase-locked loop circuit' [patent_app_type] => 1 [patent_app_number] => 8/788653 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2984 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796311.pdf [firstpage_image] =>[orig_patent_app_number] => 788653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3822784 [patent_doc_number] => 05770975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Phase-locked loop circuit having a high-speed forcible pulling-in function' [patent_app_type] => 1 [patent_app_number] => 8/788654 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2525 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770975.pdf [firstpage_image] =>[orig_patent_app_number] => 788654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3823641 [patent_doc_number] => 05789989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Delay interpolating voltage-controlled oscillator with linear transfer function' [patent_app_type] => 1 [patent_app_number] => 8/787666 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1962 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789989.pdf [firstpage_image] =>[orig_patent_app_number] => 787666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3750669 [patent_doc_number] => 05801596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Temperature compensation type quartz oscillator' [patent_app_type] => 1 [patent_app_number] => 8/765459 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 24150 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801596.pdf [firstpage_image] =>[orig_patent_app_number] => 765459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3756845 [patent_doc_number] => 05802002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Cache memory device of DRAM configuration without refresh function' [patent_app_type] => 1 [patent_app_number] => 8/784374 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4055 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802002.pdf [firstpage_image] =>[orig_patent_app_number] => 784374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015469 [patent_doc_number] => 05889440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Adaptive frequency compensation technique' [patent_app_type] => 1 [patent_app_number] => 8/784161 [patent_app_country] => US [patent_app_date] => 1997-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2531 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889440.pdf [firstpage_image] =>[orig_patent_app_number] => 784161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3750569 [patent_doc_number] => 05801589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Frequency synthesizer which suppresses a spurious' [patent_app_type] => 1 [patent_app_number] => 8/781519 [patent_app_country] => US [patent_app_date] => 1997-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 48 [patent_no_of_words] => 25857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801589.pdf [firstpage_image] =>[orig_patent_app_number] => 781519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3906037 [patent_doc_number] => 05751187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method and device for phase-modulated signals' [patent_app_type] => 1 [patent_app_number] => 8/765405 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751187.pdf [firstpage_image] =>[orig_patent_app_number] => 765405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867472 [patent_doc_number] => 05793257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Oscillator having switching capacitors and phase-locked loop employing same' [patent_app_type] => 1 [patent_app_number] => 8/778781 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7557 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793257.pdf [firstpage_image] =>[orig_patent_app_number] => 778781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3894758 [patent_doc_number] => 05777522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Electronic device for controlling a reactance value for a reactive element' [patent_app_type] => 1 [patent_app_number] => 8/775991 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4796 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777522.pdf [firstpage_image] =>[orig_patent_app_number] => 775991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3792514 [patent_doc_number] => 05818786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Layout method of semiconductor memory and content-addressable memory' [patent_app_type] => 1 [patent_app_number] => 8/771687 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 13828 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818786.pdf [firstpage_image] =>[orig_patent_app_number] => 771687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824868 [patent_doc_number] => 05812454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Nand-type flash memory device and driving method thereof' [patent_app_type] => 1 [patent_app_number] => 8/771174 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812454.pdf [firstpage_image] =>[orig_patent_app_number] => 771174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3826223 [patent_doc_number] => 05771200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/771776 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2318 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771200.pdf [firstpage_image] =>[orig_patent_app_number] => 771776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3844797 [patent_doc_number] => 05761146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Data in/out channel control circuit of semiconductor memory device having multi-bank structure' [patent_app_type] => 1 [patent_app_number] => 8/770673 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4580 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761146.pdf [firstpage_image] =>[orig_patent_app_number] => 770673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4077812 [patent_doc_number] => 05867442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Variable output voltage booster circuits and methods' [patent_app_type] => 1 [patent_app_number] => 8/772172 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2549 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867442.pdf [firstpage_image] =>[orig_patent_app_number] => 772172 [rel_patent_id] =>[rel_patent_doc_number] =>)