
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3789463
[patent_doc_number] => 05808956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Bus-line drive circuit and semiconductor storage device comprising the same'
[patent_app_type] => 1
[patent_app_number] => 8/769272
[patent_app_country] => US
[patent_app_date] => 1996-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 15089
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808956.pdf
[firstpage_image] =>[orig_patent_app_number] => 769272
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/769272 | Bus-line drive circuit and semiconductor storage device comprising the same | Dec 17, 1996 | Issued |
Array
(
[id] => 3821112
[patent_doc_number] => 05831896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/767772
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 3197
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/831/05831896.pdf
[firstpage_image] =>[orig_patent_app_number] => 767772
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767772 | Memory cell | Dec 16, 1996 | Issued |
Array
(
[id] => 3883052
[patent_doc_number] => 05838627
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Arrangement of power supply and data input/output pads in semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/768090
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 36
[patent_no_of_words] => 19717
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/838/05838627.pdf
[firstpage_image] =>[orig_patent_app_number] => 768090
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768090 | Arrangement of power supply and data input/output pads in semiconductor memory device | Dec 15, 1996 | Issued |
Array
(
[id] => 3873752
[patent_doc_number] => 05793680
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Input buffer circuit, integrated circuit device, semiconductor memory, and integrated circuit system coping with high-frequency clock signal'
[patent_app_type] => 1
[patent_app_number] => 8/766173
[patent_app_country] => US
[patent_app_date] => 1996-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 46
[patent_no_of_words] => 12907
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/793/05793680.pdf
[firstpage_image] =>[orig_patent_app_number] => 766173
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/766173 | Input buffer circuit, integrated circuit device, semiconductor memory, and integrated circuit system coping with high-frequency clock signal | Dec 11, 1996 | Issued |
Array
(
[id] => 3980491
[patent_doc_number] => 05886921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Static random access memory cell having graded channel metal oxide semiconductor transistors and method of operation'
[patent_app_type] => 1
[patent_app_number] => 8/762171
[patent_app_country] => US
[patent_app_date] => 1996-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1898
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/886/05886921.pdf
[firstpage_image] =>[orig_patent_app_number] => 762171
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762171 | Static random access memory cell having graded channel metal oxide semiconductor transistors and method of operation | Dec 8, 1996 | Issued |
Array
(
[id] => 3774983
[patent_doc_number] => 05844847
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Method and Nonvolatile semiconductor memory for repairing over-erased cells'
[patent_app_type] => 1
[patent_app_number] => 8/759673
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 6850
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/844/05844847.pdf
[firstpage_image] =>[orig_patent_app_number] => 759673
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759673 | Method and Nonvolatile semiconductor memory for repairing over-erased cells | Dec 5, 1996 | Issued |
Array
(
[id] => 3756593
[patent_doc_number] => 05801984
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Magnetic tunnel junction device with ferromagnetic multilayer having fixed magnetic moment'
[patent_app_type] => 1
[patent_app_number] => 8/757175
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 6965
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/801/05801984.pdf
[firstpage_image] =>[orig_patent_app_number] => 757175
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757175 | Magnetic tunnel junction device with ferromagnetic multilayer having fixed magnetic moment | Nov 26, 1996 | Issued |
Array
(
[id] => 3837612
[patent_doc_number] => 05784316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Non-volatile storage device'
[patent_app_type] => 1
[patent_app_number] => 8/753373
[patent_app_country] => US
[patent_app_date] => 1996-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4283
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784316.pdf
[firstpage_image] =>[orig_patent_app_number] => 753373
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/753373 | Non-volatile storage device | Nov 24, 1996 | Issued |
Array
(
[id] => 3844688
[patent_doc_number] => 05761138
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Memory devices having a flexible redundant block architecture'
[patent_app_type] => 1
[patent_app_number] => 8/754673
[patent_app_country] => US
[patent_app_date] => 1996-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6527
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/761/05761138.pdf
[firstpage_image] =>[orig_patent_app_number] => 754673
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754673 | Memory devices having a flexible redundant block architecture | Nov 20, 1996 | Issued |
Array
(
[id] => 3844478
[patent_doc_number] => 05761122
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Semiconductor memory device with program/erase verification'
[patent_app_type] => 1
[patent_app_number] => 8/749673
[patent_app_country] => US
[patent_app_date] => 1996-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 76
[patent_no_of_words] => 17779
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/761/05761122.pdf
[firstpage_image] =>[orig_patent_app_number] => 749673
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749673 | Semiconductor memory device with program/erase verification | Nov 14, 1996 | Issued |
Array
(
[id] => 3739069
[patent_doc_number] => 05703813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'DRAM having multiple column address strobe operation'
[patent_app_type] => 1
[patent_app_number] => 8/749002
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4149
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703813.pdf
[firstpage_image] =>[orig_patent_app_number] => 749002
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749002 | DRAM having multiple column address strobe operation | Nov 13, 1996 | Issued |
Array
(
[id] => 3853972
[patent_doc_number] => 05745422
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Cross-coupled bitline segments for generalized data propagation'
[patent_app_type] => 1
[patent_app_number] => 8/748076
[patent_app_country] => US
[patent_app_date] => 1996-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3397
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/745/05745422.pdf
[firstpage_image] =>[orig_patent_app_number] => 748076
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/748076 | Cross-coupled bitline segments for generalized data propagation | Nov 11, 1996 | Issued |
Array
(
[id] => 3748995
[patent_doc_number] => RE035807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Power semiconductor packaging'
[patent_app_type] => 2
[patent_app_number] => 8/743656
[patent_app_country] => US
[patent_app_date] => 1996-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 48
[patent_no_of_words] => 20258
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 314
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/035/RE035807.pdf
[firstpage_image] =>[orig_patent_app_number] => 743656
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/743656 | Power semiconductor packaging | Nov 4, 1996 | Issued |
Array
(
[id] => 3698148
[patent_doc_number] => 05691951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Staggered row line firing in single ras cycle'
[patent_app_type] => 1
[patent_app_number] => 8/743476
[patent_app_country] => US
[patent_app_date] => 1996-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4298
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/691/05691951.pdf
[firstpage_image] =>[orig_patent_app_number] => 743476
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/743476 | Staggered row line firing in single ras cycle | Nov 3, 1996 | Issued |
| 08/742366 | NEGATIVE VOLTAGE SWITCH ARCHITECTURE FOR A NONVOLATILE MEMORY | Oct 30, 1996 | Abandoned |
Array
(
[id] => 3836020
[patent_doc_number] => 05732018
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Self-contained reprogramming nonvolatile integrated circuit memory devices and methods'
[patent_app_type] => 1
[patent_app_number] => 8/739276
[patent_app_country] => US
[patent_app_date] => 1996-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10986
[patent_no_of_claims] => 14
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[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/732/05732018.pdf
[firstpage_image] =>[orig_patent_app_number] => 739276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739276 | Self-contained reprogramming nonvolatile integrated circuit memory devices and methods | Oct 28, 1996 | Issued |
Array
(
[id] => 3892766
[patent_doc_number] => 05748560
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Synchronous semiconductor memory device with auto precharge operation easily controlled'
[patent_app_type] => 1
[patent_app_number] => 8/740175
[patent_app_country] => US
[patent_app_date] => 1996-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 32
[patent_no_of_words] => 19048
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[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748560.pdf
[firstpage_image] =>[orig_patent_app_number] => 740175
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/740175 | Synchronous semiconductor memory device with auto precharge operation easily controlled | Oct 27, 1996 | Issued |
Array
(
[id] => 3753131
[patent_doc_number] => 05754466
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Ferroelectric memory having pair of reference cells'
[patent_app_type] => 1
[patent_app_number] => 8/734776
[patent_app_country] => US
[patent_app_date] => 1996-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 6184
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[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754466.pdf
[firstpage_image] =>[orig_patent_app_number] => 734776
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/734776 | Ferroelectric memory having pair of reference cells | Oct 21, 1996 | Issued |
Array
(
[id] => 3783851
[patent_doc_number] => 05774399
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Flash memory device'
[patent_app_type] => 1
[patent_app_number] => 8/730874
[patent_app_country] => US
[patent_app_date] => 1996-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2793
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774399.pdf
[firstpage_image] =>[orig_patent_app_number] => 730874
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730874 | Flash memory device | Oct 17, 1996 | Issued |
Array
(
[id] => 3900661
[patent_doc_number] => 05777922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Flash memory device'
[patent_app_type] => 1
[patent_app_number] => 8/730873
[patent_app_country] => US
[patent_app_date] => 1996-10-18
[patent_effective_date] => 0000-00-00
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[patent_words_short_claim] => 129
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/777/05777922.pdf
[firstpage_image] =>[orig_patent_app_number] => 730873
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730873 | Flash memory device | Oct 17, 1996 | Issued |