
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3638762
[patent_doc_number] => 05687116
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Programming pulse ramp control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/727875
[patent_app_country] => US
[patent_app_date] => 1996-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3667
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/687/05687116.pdf
[firstpage_image] =>[orig_patent_app_number] => 727875
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/727875 | Programming pulse ramp control circuit | Oct 8, 1996 | Issued |
Array
(
[id] => 3888942
[patent_doc_number] => 05764591
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Memory device and memory control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/724475
[patent_app_country] => US
[patent_app_date] => 1996-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 5541
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764591.pdf
[firstpage_image] =>[orig_patent_app_number] => 724475
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/724475 | Memory device and memory control circuit | Sep 30, 1996 | Issued |
Array
(
[id] => 3892007
[patent_doc_number] => 05805495
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Ferroelectric semiconductor memory and accessing method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/723275
[patent_app_country] => US
[patent_app_date] => 1996-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3722
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805495.pdf
[firstpage_image] =>[orig_patent_app_number] => 723275
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723275 | Ferroelectric semiconductor memory and accessing method therefor | Sep 29, 1996 | Issued |
Array
(
[id] => 3797977
[patent_doc_number] => 05822246
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Method and apparatus for detecting the voltage on the VCC pin'
[patent_app_type] => 1
[patent_app_number] => 8/723270
[patent_app_country] => US
[patent_app_date] => 1996-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9205
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822246.pdf
[firstpage_image] =>[orig_patent_app_number] => 723270
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723270 | Method and apparatus for detecting the voltage on the VCC pin | Sep 29, 1996 | Issued |
Array
(
[id] => 3756831
[patent_doc_number] => 05717640
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'ROM type semiconductor memory device with large operating margin'
[patent_app_type] => 1
[patent_app_number] => 8/723276
[patent_app_country] => US
[patent_app_date] => 1996-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 19
[patent_no_of_words] => 6219
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717640.pdf
[firstpage_image] =>[orig_patent_app_number] => 723276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723276 | ROM type semiconductor memory device with large operating margin | Sep 29, 1996 | Issued |
Array
(
[id] => 3891966
[patent_doc_number] => 05805492
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Analog memory for storing a QCIF image or the like as electric charge'
[patent_app_type] => 1
[patent_app_number] => 8/722572
[patent_app_country] => US
[patent_app_date] => 1996-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5957
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805492.pdf
[firstpage_image] =>[orig_patent_app_number] => 722572
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/722572 | Analog memory for storing a QCIF image or the like as electric charge | Sep 26, 1996 | Issued |
Array
(
[id] => 3837672
[patent_doc_number] => 05784320
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Method and apparatus for reducing power consumption in a memory by employing a conditional write controller'
[patent_app_type] => 1
[patent_app_number] => 8/721674
[patent_app_country] => US
[patent_app_date] => 1996-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3564
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784320.pdf
[firstpage_image] =>[orig_patent_app_number] => 721674
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721674 | Method and apparatus for reducing power consumption in a memory by employing a conditional write controller | Sep 26, 1996 | Issued |
Array
(
[id] => 3737519
[patent_doc_number] => 05694063
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'High speed I.sub.DDQ monitor circuit'
[patent_app_type] => 1
[patent_app_number] => 8/721973
[patent_app_country] => US
[patent_app_date] => 1996-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 5956
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/694/05694063.pdf
[firstpage_image] =>[orig_patent_app_number] => 721973
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721973 | High speed I.sub.DDQ monitor circuit | Sep 26, 1996 | Issued |
Array
(
[id] => 3891878
[patent_doc_number] => 05798974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Semiconductor memory device realizing high speed access and low power consumption with redundant circuit'
[patent_app_type] => 1
[patent_app_number] => 8/721075
[patent_app_country] => US
[patent_app_date] => 1996-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 73
[patent_no_of_words] => 6012
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798974.pdf
[firstpage_image] =>[orig_patent_app_number] => 721075
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721075 | Semiconductor memory device realizing high speed access and low power consumption with redundant circuit | Sep 25, 1996 | Issued |
Array
(
[id] => 3836041
[patent_doc_number] => 05732020
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Circuitry and methods for erasing EEPROM transistors'
[patent_app_type] => 1
[patent_app_number] => 8/717775
[patent_app_country] => US
[patent_app_date] => 1996-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2950
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/732/05732020.pdf
[firstpage_image] =>[orig_patent_app_number] => 717775
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/717775 | Circuitry and methods for erasing EEPROM transistors | Sep 23, 1996 | Issued |
Array
(
[id] => 4194110
[patent_doc_number] => 06021084
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Multi-bit block write in a random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/717712
[patent_app_country] => US
[patent_app_date] => 1996-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3882
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/021/06021084.pdf
[firstpage_image] =>[orig_patent_app_number] => 717712
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/717712 | Multi-bit block write in a random access memory | Sep 22, 1996 | Issued |
Array
(
[id] => 3892648
[patent_doc_number] => 05748553
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Semiconductor memory device having extended margin in latching input signal'
[patent_app_type] => 1
[patent_app_number] => 8/712875
[patent_app_country] => US
[patent_app_date] => 1996-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6836
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748553.pdf
[firstpage_image] =>[orig_patent_app_number] => 712875
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/712875 | Semiconductor memory device having extended margin in latching input signal | Sep 11, 1996 | Issued |
Array
(
[id] => 3851941
[patent_doc_number] => 05708609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Semiconductor memory device with dataline undershoot detection and reduced read access time'
[patent_app_type] => 1
[patent_app_number] => 8/708575
[patent_app_country] => US
[patent_app_date] => 1996-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4875
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708609.pdf
[firstpage_image] =>[orig_patent_app_number] => 708575
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/708575 | Semiconductor memory device with dataline undershoot detection and reduced read access time | Sep 4, 1996 | Issued |
Array
(
[id] => 3892382
[patent_doc_number] => 05805522
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Address access path control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/706373
[patent_app_country] => US
[patent_app_date] => 1996-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 7528
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/805/05805522.pdf
[firstpage_image] =>[orig_patent_app_number] => 706373
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/706373 | Address access path control circuit | Aug 29, 1996 | Issued |
Array
(
[id] => 3892675
[patent_doc_number] => 05748555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Memory address preview control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/703772
[patent_app_country] => US
[patent_app_date] => 1996-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2549
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/748/05748555.pdf
[firstpage_image] =>[orig_patent_app_number] => 703772
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703772 | Memory address preview control circuit | Aug 26, 1996 | Issued |
Array
(
[id] => 3699940
[patent_doc_number] => 05650745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'MOSFET IC with on-chip protection against oxide damage caused by plasma-induced electrical charges'
[patent_app_type] => 1
[patent_app_number] => 8/702865
[patent_app_country] => US
[patent_app_date] => 1996-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1340
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/650/05650745.pdf
[firstpage_image] =>[orig_patent_app_number] => 702865
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/702865 | MOSFET IC with on-chip protection against oxide damage caused by plasma-induced electrical charges | Aug 25, 1996 | Issued |
Array
(
[id] => 3890109
[patent_doc_number] => 05729493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Memory suitable for operation at low power supply voltages and sense amplifier therefor'
[patent_app_type] => 1
[patent_app_number] => 8/703176
[patent_app_country] => US
[patent_app_date] => 1996-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 13313
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/729/05729493.pdf
[firstpage_image] =>[orig_patent_app_number] => 703176
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703176 | Memory suitable for operation at low power supply voltages and sense amplifier therefor | Aug 22, 1996 | Issued |
Array
(
[id] => 3764929
[patent_doc_number] => 05721704
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Control gate driver circuit for a non-volatile memory and memory using same'
[patent_app_type] => 1
[patent_app_number] => 8/703174
[patent_app_country] => US
[patent_app_date] => 1996-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 13325
[patent_no_of_claims] => 25
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[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721704.pdf
[firstpage_image] =>[orig_patent_app_number] => 703174
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703174 | Control gate driver circuit for a non-volatile memory and memory using same | Aug 22, 1996 | Issued |
Array
(
[id] => 3965344
[patent_doc_number] => RE036046
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Drive circuit for inductive loads, particularly for fuel injectors'
[patent_app_type] => 2
[patent_app_number] => 8/699879
[patent_app_country] => US
[patent_app_date] => 1996-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2930
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 32
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/036/RE036046.pdf
[firstpage_image] =>[orig_patent_app_number] => 699879
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/699879 | Drive circuit for inductive loads, particularly for fuel injectors | Aug 22, 1996 | Issued |
Array
(
[id] => 3697206
[patent_doc_number] => 05696719
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Sense amplified output control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/702372
[patent_app_country] => US
[patent_app_date] => 1996-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 19
[patent_no_of_words] => 4248
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696719.pdf
[firstpage_image] =>[orig_patent_app_number] => 702372
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/702372 | Sense amplified output control circuit | Aug 22, 1996 | Issued |