Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3843790 [patent_doc_number] => 05740109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Non-linear charge pump' [patent_app_type] => 1 [patent_app_number] => 8/703173 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 13295 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740109.pdf [firstpage_image] =>[orig_patent_app_number] => 703173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703173
Non-linear charge pump Aug 22, 1996 Issued
Array ( [id] => 3897834 [patent_doc_number] => 05715206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Dynamic random access memory having sequential word line refresh' [patent_app_type] => 1 [patent_app_number] => 8/701672 [patent_app_country] => US [patent_app_date] => 1996-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1595 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715206.pdf [firstpage_image] =>[orig_patent_app_number] => 701672 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701672
Dynamic random access memory having sequential word line refresh Aug 21, 1996 Issued
Array ( [id] => 3809173 [patent_doc_number] => 05828599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Memory with electrically erasable and programmable redundancy' [patent_app_type] => 1 [patent_app_number] => 8/692571 [patent_app_country] => US [patent_app_date] => 1996-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6467 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828599.pdf [firstpage_image] =>[orig_patent_app_number] => 692571 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/692571
Memory with electrically erasable and programmable redundancy Aug 5, 1996 Issued
Array ( [id] => 3791922 [patent_doc_number] => 05818753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Electrically-erasable and programmable ROM with pulse-driven memory cell' [patent_app_type] => 1 [patent_app_number] => 8/692861 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 51 [patent_no_of_words] => 24839 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818753.pdf [firstpage_image] =>[orig_patent_app_number] => 692861 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/692861
Electrically-erasable and programmable ROM with pulse-driven memory cell Jul 29, 1996 Issued
Array ( [id] => 3824922 [patent_doc_number] => 05812458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Electrically-erasable and programmable ROM with pulse-driven memory cells' [patent_app_type] => 1 [patent_app_number] => 8/692862 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 46 [patent_no_of_words] => 20918 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812458.pdf [firstpage_image] =>[orig_patent_app_number] => 692862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/692862
Electrically-erasable and programmable ROM with pulse-driven memory cells Jul 29, 1996 Issued
Array ( [id] => 3772487 [patent_doc_number] => 05742554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Volatile memory device and method of refreshing same' [patent_app_type] => 1 [patent_app_number] => 8/685859 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6672 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742554.pdf [firstpage_image] =>[orig_patent_app_number] => 685859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/685859
Volatile memory device and method of refreshing same Jul 23, 1996 Issued
Array ( [id] => 3738982 [patent_doc_number] => 05703807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'EEPROM with enhanced reliability by selectable V.sub.PP for write and erase' [patent_app_type] => 1 [patent_app_number] => 8/684375 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3642 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703807.pdf [firstpage_image] =>[orig_patent_app_number] => 684375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684375
EEPROM with enhanced reliability by selectable V.sub.PP for write and erase Jul 18, 1996 Issued
Array ( [id] => 3774816 [patent_doc_number] => 05844839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Programmable and convertible non-volatile memory array' [patent_app_type] => 1 [patent_app_number] => 8/684962 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 7032 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844839.pdf [firstpage_image] =>[orig_patent_app_number] => 684962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684962
Programmable and convertible non-volatile memory array Jul 18, 1996 Issued
Array ( [id] => 3791171 [patent_doc_number] => 05821777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Current amplifier and data bus circuit' [patent_app_type] => 1 [patent_app_number] => 8/678858 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13879 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821777.pdf [firstpage_image] =>[orig_patent_app_number] => 678858 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678858
Current amplifier and data bus circuit Jul 11, 1996 Issued
Array ( [id] => 3732030 [patent_doc_number] => 05682351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Semiconductor memory device having an internal copy function' [patent_app_type] => 1 [patent_app_number] => 8/680572 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2790 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682351.pdf [firstpage_image] =>[orig_patent_app_number] => 680572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680572
Semiconductor memory device having an internal copy function Jul 11, 1996 Issued
Array ( [id] => 3801334 [patent_doc_number] => 05781035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Dual-differential-pair emitter-coupled logic complementary-output circuit' [patent_app_type] => 1 [patent_app_number] => 8/678780 [patent_app_country] => US [patent_app_date] => 1996-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6350 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781035.pdf [firstpage_image] =>[orig_patent_app_number] => 678780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678780
Dual-differential-pair emitter-coupled logic complementary-output circuit Jul 10, 1996 Issued
Array ( [id] => 3747419 [patent_doc_number] => 05699305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Amplifier and semiconductor memory device having the same' [patent_app_type] => 1 [patent_app_number] => 8/677364 [patent_app_country] => US [patent_app_date] => 1996-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 10906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699305.pdf [firstpage_image] =>[orig_patent_app_number] => 677364 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677364
Amplifier and semiconductor memory device having the same Jul 4, 1996 Issued
Array ( [id] => 3892334 [patent_doc_number] => 05748531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Common source line control circuit for preventing snap back breakdown' [patent_app_type] => 1 [patent_app_number] => 8/672663 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748531.pdf [firstpage_image] =>[orig_patent_app_number] => 672663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672663
Common source line control circuit for preventing snap back breakdown Jun 27, 1996 Issued
Array ( [id] => 3712953 [patent_doc_number] => 05675542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Memory bit-line pull-up scheme' [patent_app_type] => 1 [patent_app_number] => 8/671671 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5235 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675542.pdf [firstpage_image] =>[orig_patent_app_number] => 671671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671671
Memory bit-line pull-up scheme Jun 27, 1996 Issued
Array ( [id] => 3890203 [patent_doc_number] => 05729498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Reduced power consumption sram' [patent_app_type] => 1 [patent_app_number] => 8/670376 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2456 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729498.pdf [firstpage_image] =>[orig_patent_app_number] => 670376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670376
Reduced power consumption sram Jun 24, 1996 Issued
Array ( [id] => 3731941 [patent_doc_number] => 05682345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Non-volatile data storage unit method of controlling same' [patent_app_type] => 1 [patent_app_number] => 8/668398 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4000 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682345.pdf [firstpage_image] =>[orig_patent_app_number] => 668398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668398
Non-volatile data storage unit method of controlling same Jun 24, 1996 Issued
Array ( [id] => 3845884 [patent_doc_number] => 05815456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Multibank -- multiport memories and systems and methods using the same' [patent_app_type] => 1 [patent_app_number] => 8/666814 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6647 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815456.pdf [firstpage_image] =>[orig_patent_app_number] => 666814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/666814
Multibank -- multiport memories and systems and methods using the same Jun 18, 1996 Issued
Array ( [id] => 3851844 [patent_doc_number] => 05708603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/678873 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4806 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708603.pdf [firstpage_image] =>[orig_patent_app_number] => 678873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678873
Semiconductor memory device Jun 17, 1996 Issued
Array ( [id] => 3836112 [patent_doc_number] => 05732025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Output interfacing device programmable among three states for a memory in CMOS technology' [patent_app_type] => 1 [patent_app_number] => 8/661175 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5391 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732025.pdf [firstpage_image] =>[orig_patent_app_number] => 661175 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/661175
Output interfacing device programmable among three states for a memory in CMOS technology Jun 9, 1996 Issued
Array ( [id] => 3957564 [patent_doc_number] => 05982696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Memories with programmable address decoding and systems and methods using the same' [patent_app_type] => 1 [patent_app_number] => 8/659664 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6510 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982696.pdf [firstpage_image] =>[orig_patent_app_number] => 659664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/659664
Memories with programmable address decoding and systems and methods using the same Jun 5, 1996 Issued
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