Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
08/655679 HIGH DENSITY DYNAMIC BUS ROUTING SCHEME Jun 2, 1996 Abandoned
Array ( [id] => 3704422 [patent_doc_number] => 05680362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Circuit and method for accessing memory cells of a memory device' [patent_app_type] => 1 [patent_app_number] => 8/657637 [patent_app_country] => US [patent_app_date] => 1996-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6938 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680362.pdf [firstpage_image] =>[orig_patent_app_number] => 657637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657637
Circuit and method for accessing memory cells of a memory device May 29, 1996 Issued
08/653964 METHOD AND APPARATUS FOR PROGRAMMING ANTI-FUSES USING AN ISOLATED WELL PROGRAMMING CIRCUIT May 27, 1996 Abandoned
Array ( [id] => 3666867 [patent_doc_number] => 05659510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Integrated circuit devices with reliable fuse-based mode selection capability and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 8/651374 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2454 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659510.pdf [firstpage_image] =>[orig_patent_app_number] => 651374 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651374
Integrated circuit devices with reliable fuse-based mode selection capability and methods of operating same May 21, 1996 Issued
Array ( [id] => 3825178 [patent_doc_number] => 05812478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Semiconductor memory having improved data bus arrangement' [patent_app_type] => 1 [patent_app_number] => 8/651418 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8822 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812478.pdf [firstpage_image] =>[orig_patent_app_number] => 651418 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651418
Semiconductor memory having improved data bus arrangement May 21, 1996 Issued
Array ( [id] => 3706809 [patent_doc_number] => 05677877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Integrated circuit chips with multiplexed input/output pads and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 8/651375 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2875 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677877.pdf [firstpage_image] =>[orig_patent_app_number] => 651375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651375
Integrated circuit chips with multiplexed input/output pads and methods of operating same May 21, 1996 Issued
Array ( [id] => 3629636 [patent_doc_number] => 05642316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Method and apparatus of redundancy for non-volatile memory integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/653073 [patent_app_country] => US [patent_app_date] => 1996-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6340 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642316.pdf [firstpage_image] =>[orig_patent_app_number] => 653073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653073
Method and apparatus of redundancy for non-volatile memory integrated circuits May 20, 1996 Issued
Array ( [id] => 3844852 [patent_doc_number] => 05761150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Synchronous memory with pipelined write operation' [patent_app_type] => 1 [patent_app_number] => 8/651873 [patent_app_country] => US [patent_app_date] => 1996-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6605 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761150.pdf [firstpage_image] =>[orig_patent_app_number] => 651873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651873
Synchronous memory with pipelined write operation May 20, 1996 Issued
Array ( [id] => 3697878 [patent_doc_number] => 05663913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines' [patent_app_type] => 1 [patent_app_number] => 8/638373 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1798 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663913.pdf [firstpage_image] =>[orig_patent_app_number] => 638373 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638373
Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines Apr 25, 1996 Issued
Array ( [id] => 3742001 [patent_doc_number] => 05694363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Reading circuit for memory cell devices having a low supply voltage' [patent_app_type] => 1 [patent_app_number] => 8/638976 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5470 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694363.pdf [firstpage_image] =>[orig_patent_app_number] => 638976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638976
Reading circuit for memory cell devices having a low supply voltage Apr 24, 1996 Issued
Array ( [id] => 3733098 [patent_doc_number] => 05673225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Word line voltage boosting circuit and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/623772 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4284 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673225.pdf [firstpage_image] =>[orig_patent_app_number] => 623772 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623772
Word line voltage boosting circuit and method thereof Mar 28, 1996 Issued
Array ( [id] => 3659050 [patent_doc_number] => 05684735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Semiconductor memory cell' [patent_app_type] => 1 [patent_app_number] => 8/623371 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2907 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684735.pdf [firstpage_image] =>[orig_patent_app_number] => 623371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623371
Semiconductor memory cell Mar 27, 1996 Issued
Array ( [id] => 3892201 [patent_doc_number] => 05748522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Memory element of the master-slave flip-flop type, constructed by CMOS technology' [patent_app_type] => 1 [patent_app_number] => 8/618970 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 5115 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748522.pdf [firstpage_image] =>[orig_patent_app_number] => 618970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/618970
Memory element of the master-slave flip-flop type, constructed by CMOS technology Mar 19, 1996 Issued
Array ( [id] => 3897784 [patent_doc_number] => 05715203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Semiconductor memory device and automatic bit line precharge method therefor' [patent_app_type] => 1 [patent_app_number] => 8/617073 [patent_app_country] => US [patent_app_date] => 1996-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4962 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715203.pdf [firstpage_image] =>[orig_patent_app_number] => 617073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617073
Semiconductor memory device and automatic bit line precharge method therefor Mar 17, 1996 Issued
Array ( [id] => 3699224 [patent_doc_number] => 05604710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Arrangement of power supply and data input/output pads in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/616734 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 36 [patent_no_of_words] => 19717 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604710.pdf [firstpage_image] =>[orig_patent_app_number] => 616734 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616734
Arrangement of power supply and data input/output pads in semiconductor memory device Mar 14, 1996 Issued
Array ( [id] => 3678583 [patent_doc_number] => 05600606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same' [patent_app_type] => 1 [patent_app_number] => 8/612113 [patent_app_country] => US [patent_app_date] => 1996-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5564 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600606.pdf [firstpage_image] =>[orig_patent_app_number] => 612113 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/612113
Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same Mar 6, 1996 Issued
Array ( [id] => 3728574 [patent_doc_number] => 05682115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Active pull-up voltage spike reducer' [patent_app_type] => 1 [patent_app_number] => 8/611893 [patent_app_country] => US [patent_app_date] => 1996-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1431 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682115.pdf [firstpage_image] =>[orig_patent_app_number] => 611893 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611893
Active pull-up voltage spike reducer Mar 5, 1996 Issued
Array ( [id] => 3700861 [patent_doc_number] => 05596290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Direct frequency synthesizer having moderate bandwidth' [patent_app_type] => 1 [patent_app_number] => 8/607924 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4003 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596290.pdf [firstpage_image] =>[orig_patent_app_number] => 607924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607924
Direct frequency synthesizer having moderate bandwidth Feb 27, 1996 Issued
Array ( [id] => 3633038 [patent_doc_number] => 05602770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Associative memory device' [patent_app_type] => 1 [patent_app_number] => 8/594673 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 14098 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602770.pdf [firstpage_image] =>[orig_patent_app_number] => 594673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/594673
Associative memory device Feb 1, 1996 Issued
08/594747 METHOD OF ISOLATING A SRAM CELL Jan 30, 1996 Abandoned
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