Search

Trong Q. Phan

Examiner (ID: 8660, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2504, 2827, 2818, 2511, 2824, 2825, 2899
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6157357 [patent_doc_number] => 20110157984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'BLOCK DECODER OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/982070 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3288 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20110157984.pdf [firstpage_image] =>[orig_patent_app_number] => 12982070 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982070
Block decoder of semiconductor memory device Dec 29, 2010 Issued
Array ( [id] => 7650072 [patent_doc_number] => 20110299341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD OF PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/982324 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20110299341.pdf [firstpage_image] =>[orig_patent_app_number] => 12982324 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982324
Method of programming a semiconductor memory device Dec 29, 2010 Issued
Array ( [id] => 9403188 [patent_doc_number] => 08693248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Nonvolatile data storage devices, program methods thereof, and memory systems including the same' [patent_app_type] => utility [patent_app_number] => 12/981934 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981934
Nonvolatile data storage devices, program methods thereof, and memory systems including the same Dec 29, 2010 Issued
Array ( [id] => 8739723 [patent_doc_number] => 08411503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Method of operating semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/982302 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8740 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982302 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982302
Method of operating semiconductor memory device Dec 29, 2010 Issued
Array ( [id] => 7560112 [patent_doc_number] => 20110273944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/982274 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5736 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20110273944.pdf [firstpage_image] =>[orig_patent_app_number] => 12982274 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982274
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME Dec 29, 2010 Abandoned
Array ( [id] => 6100967 [patent_doc_number] => 20110164459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'LIST STRUCTURE CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/980884 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9485 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20110164459.pdf [firstpage_image] =>[orig_patent_app_number] => 12980884 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/980884
List structure control circuit Dec 28, 2010 Issued
Array ( [id] => 7719100 [patent_doc_number] => 20120008435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'DELAY LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/981052 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4009 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20120008435.pdf [firstpage_image] =>[orig_patent_app_number] => 12981052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981052
Delay locked loop Dec 28, 2010 Issued
Array ( [id] => 8136807 [patent_doc_number] => 20120092947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'FUSE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/981290 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20120092947.pdf [firstpage_image] =>[orig_patent_app_number] => 12981290 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981290
Fuse circuit and memory device including the same Dec 28, 2010 Issued
Array ( [id] => 7551900 [patent_doc_number] => 08064237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Identifying and accessing individual memory devices in a memory channel' [patent_app_type] => utility [patent_app_number] => 12/974862 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 21589 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/064/08064237.pdf [firstpage_image] =>[orig_patent_app_number] => 12974862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/974862
Identifying and accessing individual memory devices in a memory channel Dec 20, 2010 Issued
Array ( [id] => 6123413 [patent_doc_number] => 20110085376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'Shunted Phase Change Memory' [patent_app_type] => utility [patent_app_number] => 12/969756 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1359 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085376.pdf [firstpage_image] =>[orig_patent_app_number] => 12969756 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/969756
Shunted phase change memory Dec 15, 2010 Issued
Array ( [id] => 7507154 [patent_doc_number] => 08036030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Multi-level cell copyback program method in a non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 12/962570 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 10942 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/036/08036030.pdf [firstpage_image] =>[orig_patent_app_number] => 12962570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962570
Multi-level cell copyback program method in a non-volatile memory device Dec 6, 2010 Issued
Array ( [id] => 7764866 [patent_doc_number] => 20120033509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'Memory data reading and writing technique' [patent_app_type] => utility [patent_app_number] => 12/927674 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4660 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20120033509.pdf [firstpage_image] =>[orig_patent_app_number] => 12927674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/927674
Memory data reading and writing technique Nov 21, 2010 Abandoned
Array ( [id] => 8195329 [patent_doc_number] => 20120120719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'NON-VOLATILE MAGNETIC TUNNEL JUNCTION TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/945848 [patent_app_country] => US [patent_app_date] => 2010-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120719.pdf [firstpage_image] =>[orig_patent_app_number] => 12945848 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/945848
Non-volatile magnetic tunnel junction transistor Nov 12, 2010 Issued
Array ( [id] => 8189106 [patent_doc_number] => 20120117307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'NON-VOLATILE MEMORY (NVM) ERASE OPERATION WITH BROWNOUT RECOVERY TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 12/942260 [patent_app_country] => US [patent_app_date] => 2010-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117307.pdf [firstpage_image] =>[orig_patent_app_number] => 12942260 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/942260
Non-volatile memory (NVM) erase operation with brownout recovery technique Nov 8, 2010 Issued
Array ( [id] => 10846124 [patent_doc_number] => 08873314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Circuits and methods for providing data to and from arrays of memory cells' [patent_app_type] => utility [patent_app_number] => 12/940852 [patent_app_country] => US [patent_app_date] => 2010-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3647 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12940852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/940852
Circuits and methods for providing data to and from arrays of memory cells Nov 4, 2010 Issued
Array ( [id] => 8169505 [patent_doc_number] => 20120106287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Memory Arrangement for Accessing Matrices' [patent_app_type] => utility [patent_app_number] => 12/939010 [patent_app_country] => US [patent_app_date] => 2010-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6726 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20120106287.pdf [firstpage_image] =>[orig_patent_app_number] => 12939010 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/939010
Memory arrangement for accessing matrices Nov 2, 2010 Issued
Array ( [id] => 8169422 [patent_doc_number] => 20120106239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Magnetic Memory Element With Multi-Domain Storage Layer' [patent_app_type] => utility [patent_app_number] => 12/938424 [patent_app_country] => US [patent_app_date] => 2010-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20120106239.pdf [firstpage_image] =>[orig_patent_app_number] => 12938424 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938424
Magnetic memory element with multi-domain storage layer Nov 2, 2010 Issued
Array ( [id] => 6069265 [patent_doc_number] => 20110044114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'APPARATUS AND METHOD FOR BIT LINES DISCHARGING AND SENSING' [patent_app_type] => utility [patent_app_number] => 12/938996 [patent_app_country] => US [patent_app_date] => 2010-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20110044114.pdf [firstpage_image] =>[orig_patent_app_number] => 12938996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938996
APPARATUS AND METHOD FOR BIT LINES DISCHARGING AND SENSING Nov 2, 2010 Abandoned
Array ( [id] => 7783177 [patent_doc_number] => 20120044733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'Single Device Driver Circuit to Control Three-Dimensional Memory Element Array' [patent_app_type] => utility [patent_app_number] => 12/938028 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 14562 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20120044733.pdf [firstpage_image] =>[orig_patent_app_number] => 12938028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938028
Single device driver circuit to control three-dimensional memory element array Nov 1, 2010 Issued
Array ( [id] => 8176701 [patent_doc_number] => 20120110368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA' [patent_app_type] => utility [patent_app_number] => 12/938130 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3640 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110368.pdf [firstpage_image] =>[orig_patent_app_number] => 12938130 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938130
Data paths using a first signal to capture data and a second signal to output data and methods for providing data Nov 1, 2010 Issued
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