
Trong Q. Phan
Examiner (ID: 8660, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2504, 2827, 2818, 2511, 2824, 2825, 2899 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6157357
[patent_doc_number] => 20110157984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'BLOCK DECODER OF SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/982070
[patent_app_country] => US
[patent_app_date] => 2010-12-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/982070 | Block decoder of semiconductor memory device | Dec 29, 2010 | Issued |
Array
(
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[patent_doc_number] => 20110299341
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[patent_kind] => A1
[patent_issue_date] => 2011-12-08
[patent_title] => 'METHOD OF PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE'
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[patent_app_date] => 2010-12-30
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Array
(
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[patent_kind] => B2
[patent_issue_date] => 2014-04-08
[patent_title] => 'Nonvolatile data storage devices, program methods thereof, and memory systems including the same'
[patent_app_type] => utility
[patent_app_number] => 12/981934
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[patent_app_date] => 2010-12-30
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Array
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[patent_issue_date] => 2013-04-02
[patent_title] => 'Method of operating semiconductor memory device'
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[patent_app_number] => 12/982302
[patent_app_country] => US
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Array
(
[id] => 7560112
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[patent_issue_date] => 2011-11-10
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME'
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Array
(
[id] => 6100967
[patent_doc_number] => 20110164459
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[patent_kind] => A1
[patent_issue_date] => 2011-07-07
[patent_title] => 'LIST STRUCTURE CONTROL CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/980884
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[patent_app_date] => 2010-12-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/980884 | List structure control circuit | Dec 28, 2010 | Issued |
Array
(
[id] => 7719100
[patent_doc_number] => 20120008435
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[patent_kind] => A1
[patent_issue_date] => 2012-01-12
[patent_title] => 'DELAY LOCKED LOOP'
[patent_app_type] => utility
[patent_app_number] => 12/981052
[patent_app_country] => US
[patent_app_date] => 2010-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0008/20120008435.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/981052 | Delay locked loop | Dec 28, 2010 | Issued |
Array
(
[id] => 8136807
[patent_doc_number] => 20120092947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-19
[patent_title] => 'FUSE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/981290
[patent_app_country] => US
[patent_app_date] => 2010-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0092/20120092947.pdf
[firstpage_image] =>[orig_patent_app_number] => 12981290
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/981290 | Fuse circuit and memory device including the same | Dec 28, 2010 | Issued |
Array
(
[id] => 7551900
[patent_doc_number] => 08064237
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Identifying and accessing individual memory devices in a memory channel'
[patent_app_type] => utility
[patent_app_number] => 12/974862
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[pdf_file] => patents/08/064/08064237.pdf
[firstpage_image] =>[orig_patent_app_number] => 12974862
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/974862 | Identifying and accessing individual memory devices in a memory channel | Dec 20, 2010 | Issued |
Array
(
[id] => 6123413
[patent_doc_number] => 20110085376
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[patent_issue_date] => 2011-04-14
[patent_title] => 'Shunted Phase Change Memory'
[patent_app_type] => utility
[patent_app_number] => 12/969756
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[patent_app_date] => 2010-12-16
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/969756 | Shunted phase change memory | Dec 15, 2010 | Issued |
Array
(
[id] => 7507154
[patent_doc_number] => 08036030
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[patent_issue_date] => 2011-10-11
[patent_title] => 'Multi-level cell copyback program method in a non-volatile memory device'
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[pdf_file] => patents/08/036/08036030.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/962570 | Multi-level cell copyback program method in a non-volatile memory device | Dec 6, 2010 | Issued |
Array
(
[id] => 7764866
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[patent_issue_date] => 2012-02-09
[patent_title] => 'Memory data reading and writing technique'
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Array
(
[id] => 8195329
[patent_doc_number] => 20120120719
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'NON-VOLATILE MAGNETIC TUNNEL JUNCTION TRANSISTOR'
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[pdf_file] => publications/A1/0120/20120120719.pdf
[firstpage_image] =>[orig_patent_app_number] => 12945848
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/945848 | Non-volatile magnetic tunnel junction transistor | Nov 12, 2010 | Issued |
Array
(
[id] => 8189106
[patent_doc_number] => 20120117307
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[patent_title] => 'NON-VOLATILE MEMORY (NVM) ERASE OPERATION WITH BROWNOUT RECOVERY TECHNIQUE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/942260 | Non-volatile memory (NVM) erase operation with brownout recovery technique | Nov 8, 2010 | Issued |
Array
(
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[patent_title] => 'Circuits and methods for providing data to and from arrays of memory cells'
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Array
(
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Array
(
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Array
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Array
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Array
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