Search

Trong Q. Phan

Examiner (ID: 2100, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2899, 2504, 2818, 2825, 2827, 2824
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11551349 [patent_doc_number] => 09620203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Nonvolatile memory integrated circuit with built-in redundancy' [patent_app_type] => utility [patent_app_number] => 14/849047 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 7993 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849047
Nonvolatile memory integrated circuit with built-in redundancy Sep 8, 2015 Issued
Array ( [id] => 11096283 [patent_doc_number] => 20160293252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/848279 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/848279
SEMICONDUCTOR STORAGE DEVICE Sep 7, 2015 Abandoned
Array ( [id] => 10495084 [patent_doc_number] => 20150380106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'MAGNETIC MEMORY DEVICES AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/846483 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10760 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846483 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/846483
MAGNETIC MEMORY DEVICES AND SYSTEMS Sep 3, 2015 Abandoned
Array ( [id] => 11096282 [patent_doc_number] => 20160293251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/846291 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846291 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/846291
SEMICONDUCTOR MEMORY DEVICE Sep 3, 2015 Abandoned
Array ( [id] => 11475269 [patent_doc_number] => 20170062052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) WITH PROGRAMMABLE RESISTIVE ELEMENTS' [patent_app_type] => utility [patent_app_number] => 14/833287 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833287 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833287
Ternary content addressable memory (TCAM) with programmable resistive elements Aug 23, 2015 Issued
Array ( [id] => 11265733 [patent_doc_number] => 09490034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-08 [patent_title] => 'Centralized memory repair block' [patent_app_type] => utility [patent_app_number] => 14/829491 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6337 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829491
Centralized memory repair block Aug 17, 2015 Issued
Array ( [id] => 10479152 [patent_doc_number] => 20150364169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'CIRCUITS AND TECHNIQUES TO COMPENSATE MEMORY ACCESS SIGNALS FOR VARIATIONS OF PARAMETERS IN MULTIPLE LAYERS OF MEMORY' [patent_app_type] => utility [patent_app_number] => 14/827292 [patent_app_country] => US [patent_app_date] => 2015-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827292
Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory Aug 14, 2015 Issued
Array ( [id] => 10802525 [patent_doc_number] => 20160148682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'MEMORY DEVICE REDUCING TEST TIME AND COMPUTING SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/823513 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14823513 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/823513
Memory device reducing test time and computing system including the same Aug 10, 2015 Issued
Array ( [id] => 11279534 [patent_doc_number] => 09496015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-15 [patent_title] => 'Array structure having local decoders in an electronic device' [patent_app_type] => utility [patent_app_number] => 14/822941 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3227 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822941 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/822941
Array structure having local decoders in an electronic device Aug 10, 2015 Issued
Array ( [id] => 11079045 [patent_doc_number] => 20160276009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON WRITE ERROR RATE (WER) TO IMPROVE WER YIELD, AND RELATED METHODS AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/818809 [patent_app_country] => US [patent_app_date] => 2015-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14818809 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/818809
Adjusting resistive memory write driver strength based on write error rate (WER) to improve WER yield, and related methods and systems Aug 4, 2015 Issued
Array ( [id] => 11096272 [patent_doc_number] => 20160293240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'A MAGNETIC MEMORY CELL STRUCTURE WITH SPIN DEVICE ELEMENTS AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/815217 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 20111 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815217 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/815217
Magnetic memory cell structure with spin device elements and method of operating the same Jul 30, 2015 Issued
Array ( [id] => 10696638 [patent_doc_number] => 20160042785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'MEMORY DEVICE INCLUDING REFERENCE VOLTAGE GENERATOR' [patent_app_type] => utility [patent_app_number] => 14/793053 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10402 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793053 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793053
Memory device of a single-ended bitline structure including reference voltage generator Jul 6, 2015 Issued
Array ( [id] => 10417890 [patent_doc_number] => 20150302901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORT' [patent_app_type] => utility [patent_app_number] => 14/753607 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11315 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14753607 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/753607
Single package dual channel memory with co-support Jun 28, 2015 Issued
Array ( [id] => 11233530 [patent_doc_number] => 09460761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Lower power sense amplifier for reading non-volatile memory cells' [patent_app_type] => utility [patent_app_number] => 14/751701 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 8606 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751701 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751701
Lower power sense amplifier for reading non-volatile memory cells Jun 25, 2015 Issued
Array ( [id] => 13681927 [patent_doc_number] => 20160379700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => MAGNETIC STORAGE CELL MEMORY WITH BACK HOP-PREVENTION [patent_app_type] => utility [patent_app_number] => 14/751801 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751801 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751801
Magnetic storage cell memory with back hop-prevention Jun 25, 2015 Issued
Array ( [id] => 10771964 [patent_doc_number] => 20160118120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'RESISTIVE MEMORY SYSTEM, DRIVER CIRCUIT THEREOF AND METHOD FOR SETTING RESISTANCE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/749651 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8294 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14749651 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/749651
Resistive memory system, driver circuit thereof and method for setting resistance thereof Jun 24, 2015 Issued
Array ( [id] => 11207689 [patent_doc_number] => 09437319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-06 [patent_title] => 'Method for programming non-volatile memory with reduced bit line interference and associated device' [patent_app_type] => utility [patent_app_number] => 14/750065 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750065 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750065
Method for programming non-volatile memory with reduced bit line interference and associated device Jun 24, 2015 Issued
Array ( [id] => 10624208 [patent_doc_number] => 09343156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Balancing programming speeds of memory cells in a 3D stacked memory' [patent_app_type] => utility [patent_app_number] => 14/750250 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 16573 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750250
Balancing programming speeds of memory cells in a 3D stacked memory Jun 24, 2015 Issued
Array ( [id] => 13681937 [patent_doc_number] => 20160379705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => APPARATUSES AND SYSTEMS FOR INCREASING A SPEED OF REMOVAL OF DATA STORED IN A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 14/748009 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14748009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/748009
Apparatuses and systems for increasing a speed of removal of data stored in a memory cell Jun 22, 2015 Issued
Array ( [id] => 11253665 [patent_doc_number] => 09479183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-25 [patent_title] => 'Memory storage device having clock and data recovery circuit' [patent_app_type] => utility [patent_app_number] => 14/745470 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8771 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14745470 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/745470
Memory storage device having clock and data recovery circuit Jun 21, 2015 Issued
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