Trong Q. Phan

Array ( [id] => 6494693 [patent_doc_number] => 20100259967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/742538 [patent_app_country] => US [patent_app_date] => 2008-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9316 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259967.pdf [firstpage_image] =>[orig_patent_app_number] => 12742538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4522152 [patent_doc_number] => 07911836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Data restoration in case of page-programming failure' [patent_app_type] => utility [patent_app_number] => 12/275901 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4902 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/911/07911836.pdf [firstpage_image] =>[orig_patent_app_number] => 12275901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5561621 [patent_doc_number] => 20090134473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/273846 [patent_app_country] => US [patent_app_date] => 2008-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9287 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134473.pdf [firstpage_image] =>[orig_patent_app_number] => 12273846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8539392 [patent_doc_number] => 08315115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Method for testing a main memory' [patent_app_type] => utility [patent_app_number] => 12/742962 [patent_app_country] => US [patent_app_date] => 2008-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5912 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12742962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7507131 [patent_doc_number] => 08036014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Phase change memory program method without over-reset' [patent_app_type] => utility [patent_app_number] => 12/266222 [patent_app_country] => US [patent_app_date] => 2008-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 9871 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/036/08036014.pdf [firstpage_image] =>[orig_patent_app_number] => 12266222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5408696 [patent_doc_number] => 20090122594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/265988 [patent_app_country] => US [patent_app_date] => 2008-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20090122594.pdf [firstpage_image] =>[orig_patent_app_number] => 12265988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5263586 [patent_doc_number] => 20090116271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'MEMORY' [patent_app_type] => utility [patent_app_number] => 12/266332 [patent_app_country] => US [patent_app_date] => 2008-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20090116271.pdf [firstpage_image] =>[orig_patent_app_number] => 12266332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6310050 [patent_doc_number] => 20100110775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Word Line Voltage Control in STT-MRAM' [patent_app_type] => utility [patent_app_number] => 12/265044 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20100110775.pdf [firstpage_image] =>[orig_patent_app_number] => 12265044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7812321 [patent_doc_number] => 08134856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Data protection scheme during power-up in spin transfer torque magnetoresistive random access memory' [patent_app_type] => utility [patent_app_number] => 12/265068 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3714 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/134/08134856.pdf [firstpage_image] =>[orig_patent_app_number] => 12265068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5421128 [patent_doc_number] => 20090147583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING MAT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/265486 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20090147583.pdf [firstpage_image] =>[orig_patent_app_number] => 12265486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4515095 [patent_doc_number] => 07916513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Non-destructive read back for ferroelectric data storage device' [patent_app_type] => utility [patent_app_number] => 12/265418 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/916/07916513.pdf [firstpage_image] =>[orig_patent_app_number] => 12265418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5263601 [patent_doc_number] => 20090116286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE' [patent_app_type] => utility [patent_app_number] => 12/264886 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18239 [patent_no_of_claims] => 97 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20090116286.pdf [firstpage_image] =>[orig_patent_app_number] => 12264886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5301801 [patent_doc_number] => 20090296453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Semiconductor Memory Apparatus' [patent_app_type] => utility [patent_app_number] => 12/264832 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5170 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20090296453.pdf [firstpage_image] =>[orig_patent_app_number] => 12264832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5402656 [patent_doc_number] => 20090237970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/264356 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237970.pdf [firstpage_image] =>[orig_patent_app_number] => 12264356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6331198 [patent_doc_number] => 20100115224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'MEMORY APPARATUSES WITH LOW SUPPLY VOLTAGES' [patent_app_type] => utility [patent_app_number] => 12/262070 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4392 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20100115224.pdf [firstpage_image] =>[orig_patent_app_number] => 12262070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5335785 [patent_doc_number] => 20090052249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 12/251894 [patent_app_country] => US [patent_app_date] => 2008-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11244 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20090052249.pdf [firstpage_image] =>[orig_patent_app_number] => 12251894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 144238 [patent_doc_number] => 07688661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Semiconductor memory device, and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 12/234969 [patent_app_country] => US [patent_app_date] => 2008-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 19329 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688661.pdf [firstpage_image] =>[orig_patent_app_number] => 12234969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5289251 [patent_doc_number] => 20090021981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'NONVOLATILE MEMORY DEVICE INCLUDING CIRCUIT FORMED OF THIN FILM TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/211380 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12526 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20090021981.pdf [firstpage_image] =>[orig_patent_app_number] => 12211380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5295138 [patent_doc_number] => 20090010064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'NAND FLASH CELL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/211175 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12146 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20090010064.pdf [firstpage_image] =>[orig_patent_app_number] => 12211175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6331527 [patent_doc_number] => 20100246240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'SEMICONDUCTOR DEVICE CONFIGURATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/742018 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7328 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20100246240.pdf [firstpage_image] =>[orig_patent_app_number] => 12742018 [rel_patent_id] =>[rel_patent_doc_number] =>)