Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4480773 [patent_doc_number] => 07869248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Bit line decoder architecture for NOR-type memory array' [patent_app_type] => utility [patent_app_number] => 12/231963 [patent_app_country] => US [patent_app_date] => 2008-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12569 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/869/07869248.pdf [firstpage_image] =>[orig_patent_app_number] => 12231963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/231963
Bit line decoder architecture for NOR-type memory array Sep 7, 2008 Issued
Array ( [id] => 4480770 [patent_doc_number] => 07869247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Bit line decoder architecture for NOR-type memory array' [patent_app_type] => utility [patent_app_number] => 12/231959 [patent_app_country] => US [patent_app_date] => 2008-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12569 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/869/07869247.pdf [firstpage_image] =>[orig_patent_app_number] => 12231959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/231959
Bit line decoder architecture for NOR-type memory array Sep 7, 2008 Issued
Array ( [id] => 4467786 [patent_doc_number] => 07936581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Bit line decoder architecture for nor-type memory array' [patent_app_type] => utility [patent_app_number] => 12/231954 [patent_app_country] => US [patent_app_date] => 2008-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12569 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936581.pdf [firstpage_image] =>[orig_patent_app_number] => 12231954 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/231954
Bit line decoder architecture for nor-type memory array Sep 7, 2008 Issued
Array ( [id] => 5295154 [patent_doc_number] => 20090010080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/201922 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19182 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20090010080.pdf [firstpage_image] =>[orig_patent_app_number] => 12201922 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201922
Semiconductor memory device, and method of controlling the same Aug 28, 2008 Issued
Array ( [id] => 8423170 [patent_doc_number] => 08279661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Magnetic memory element, driving method for the same, and nonvolatile storage device' [patent_app_type] => utility [patent_app_number] => 12/734292 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 9770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12734292 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/734292
Magnetic memory element, driving method for the same, and nonvolatile storage device Aug 27, 2008 Issued
Array ( [id] => 4564774 [patent_doc_number] => 07821814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/222753 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 8738 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821814.pdf [firstpage_image] =>[orig_patent_app_number] => 12222753 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222753
Semiconductor memory device Aug 14, 2008 Issued
Array ( [id] => 16011 [patent_doc_number] => 07808820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage' [patent_app_type] => utility [patent_app_number] => 12/190128 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 13830 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808820.pdf [firstpage_image] =>[orig_patent_app_number] => 12190128 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/190128
Parallel programming of multiple-bit-per-cell memory cells by controlling program pulsewidth and programming voltage Aug 11, 2008 Issued
Array ( [id] => 4777371 [patent_doc_number] => 20080285369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'BLOCK ERASE FOR VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/183646 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20080285369.pdf [firstpage_image] =>[orig_patent_app_number] => 12183646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/183646
Block erase for volatile memory Jul 30, 2008 Issued
Array ( [id] => 4858132 [patent_doc_number] => 20080266982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/168786 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2501 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266982.pdf [firstpage_image] =>[orig_patent_app_number] => 12168786 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168786
CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES Jul 6, 2008 Abandoned
Array ( [id] => 4598570 [patent_doc_number] => 07983069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Write operations for phase-change-material memory' [patent_app_type] => utility [patent_app_number] => 12/146128 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3636 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/983/07983069.pdf [firstpage_image] =>[orig_patent_app_number] => 12146128 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146128
Write operations for phase-change-material memory Jun 24, 2008 Issued
Array ( [id] => 36069 [patent_doc_number] => 07787284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Integrated circuit chip with improved array stability' [patent_app_type] => utility [patent_app_number] => 12/133450 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787284.pdf [firstpage_image] =>[orig_patent_app_number] => 12133450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133450
Integrated circuit chip with improved array stability Jun 4, 2008 Issued
Array ( [id] => 4438846 [patent_doc_number] => 07898883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method for controlling access of a memory' [patent_app_type] => utility [patent_app_number] => 12/128632 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1683 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898883.pdf [firstpage_image] =>[orig_patent_app_number] => 12128632 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128632
Method for controlling access of a memory May 28, 2008 Issued
Array ( [id] => 5301862 [patent_doc_number] => 20090296514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'METHOD FOR ACCESSING A MEMORY CHIP' [patent_app_type] => utility [patent_app_number] => 12/128618 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3140 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20090296514.pdf [firstpage_image] =>[orig_patent_app_number] => 12128618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128618
METHOD FOR ACCESSING A MEMORY CHIP May 28, 2008 Abandoned
Array ( [id] => 5519994 [patent_doc_number] => 20090027975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'METHOD FOR DRIVING PHASE CHANGE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/127988 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4579 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027975.pdf [firstpage_image] =>[orig_patent_app_number] => 12127988 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127988
Method for driving phase change memory device May 27, 2008 Issued
Array ( [id] => 5507048 [patent_doc_number] => 20090080255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/128184 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6464 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080255.pdf [firstpage_image] =>[orig_patent_app_number] => 12128184 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128184
Nonvolatile semiconductor memory device May 27, 2008 Issued
Array ( [id] => 144500 [patent_doc_number] => 07692966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Nonvolatile semiconductor memory device having assist gate' [patent_app_type] => utility [patent_app_number] => 12/153927 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 48 [patent_no_of_words] => 17040 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/692/07692966.pdf [firstpage_image] =>[orig_patent_app_number] => 12153927 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153927
Nonvolatile semiconductor memory device having assist gate May 27, 2008 Issued
Array ( [id] => 5574170 [patent_doc_number] => 20090141531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'ASSOCIATIVE MEMORY AND SEARCHING SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/128126 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11821 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20090141531.pdf [firstpage_image] =>[orig_patent_app_number] => 12128126 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128126
Associative memory and searching system using the same May 27, 2008 Issued
Array ( [id] => 4709614 [patent_doc_number] => 20080298140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'MEMORY STRUCTURE WITH WORD LINE BUFFERS' [patent_app_type] => utility [patent_app_number] => 12/128122 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10249 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20080298140.pdf [firstpage_image] =>[orig_patent_app_number] => 12128122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128122
Memory structure with word line buffers May 27, 2008 Issued
Array ( [id] => 4790768 [patent_doc_number] => 20080291741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'BIT LINE DECODER ARCHITECTURE FOR NOR-TYPE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/127326 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12528 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20080291741.pdf [firstpage_image] =>[orig_patent_app_number] => 12127326 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127326
Bit line decoder architecture for NOR-type memory array May 26, 2008 Issued
Array ( [id] => 4565284 [patent_doc_number] => 07821861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Memory device and refresh method thereof' [patent_app_type] => utility [patent_app_number] => 12/127020 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7501 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821861.pdf [firstpage_image] =>[orig_patent_app_number] => 12127020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127020
Memory device and refresh method thereof May 26, 2008 Issued
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