Trong Q. Phan

Array ( [id] => 4531687 [patent_doc_number] => 07952928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Increasing read throughput in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/127136 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 11019 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952928.pdf [firstpage_image] =>[orig_patent_app_number] => 12127136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4577383 [patent_doc_number] => 07848174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Memory word-line tracking scheme' [patent_app_type] => utility [patent_app_number] => 12/126780 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2850 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/848/07848174.pdf [firstpage_image] =>[orig_patent_app_number] => 12126780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4737671 [patent_doc_number] => 20080231323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'INTEGRATED CIRCUIT CHIP WITH IMPROVED ARRAY STABILITY' [patent_app_type] => utility [patent_app_number] => 12/109401 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20080231323.pdf [firstpage_image] =>[orig_patent_app_number] => 12109401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5402684 [patent_doc_number] => 20090237998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Adaptive Algorithm in Cache Operation with Dynamic Data Latch Requirements' [patent_app_type] => utility [patent_app_number] => 12/051462 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3469 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237998.pdf [firstpage_image] =>[orig_patent_app_number] => 12051462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4737708 [patent_doc_number] => 20080231360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'ARRANGEMENT OF SIGNAL LINE PAIRS AND AMPLIFIERS' [patent_app_type] => utility [patent_app_number] => 12/051284 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8748 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20080231360.pdf [firstpage_image] =>[orig_patent_app_number] => 12051284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4467790 [patent_doc_number] => 07936582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-03 [patent_title] => 'E-fuse read circuit with dual comparators' [patent_app_type] => utility [patent_app_number] => 12/051806 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936582.pdf [firstpage_image] =>[orig_patent_app_number] => 12051806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7969937 [patent_doc_number] => 07940543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Low power synchronous memory command address scheme' [patent_app_type] => utility [patent_app_number] => 12/050950 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1531 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940543.pdf [firstpage_image] =>[orig_patent_app_number] => 12050950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5402685 [patent_doc_number] => 20090237999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Different Combinations of Wordline Order and Look-Ahead Read to Improve Non-Volatile Memory Performance' [patent_app_type] => utility [patent_app_number] => 12/051492 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4585 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20090237999.pdf [firstpage_image] =>[orig_patent_app_number] => 12051492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4738503 [patent_doc_number] => 20080232155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'MOLECULAR BATTERY MEMORY DEVICE AND DATA PROCESSING SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/051022 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6120 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232155.pdf [firstpage_image] =>[orig_patent_app_number] => 12051022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4738529 [patent_doc_number] => 20080232181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/050386 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8699 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232181.pdf [firstpage_image] =>[orig_patent_app_number] => 12050386 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4581039 [patent_doc_number] => 07855909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-21 [patent_title] => 'Calibrating page borders in a phase-change memory' [patent_app_type] => utility [patent_app_number] => 12/050604 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5489 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855909.pdf [firstpage_image] =>[orig_patent_app_number] => 12050604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 46564 [patent_doc_number] => 07778105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Memory with write port configured for double pump write' [patent_app_type] => utility [patent_app_number] => 12/049798 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4316 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/778/07778105.pdf [firstpage_image] =>[orig_patent_app_number] => 12049798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 56378 [patent_doc_number] => 07768860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Semiconductor memory device for reducing peak current during refresh operation' [patent_app_type] => utility [patent_app_number] => 12/075702 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3544 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768860.pdf [firstpage_image] =>[orig_patent_app_number] => 12075702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4750917 [patent_doc_number] => 20080158988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD AND APPARATUS FOR SENSING FLASH MEMORY USING DELTA SIGMA MODULATION' [patent_app_type] => utility [patent_app_number] => 12/046571 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3766 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20080158988.pdf [firstpage_image] =>[orig_patent_app_number] => 12046571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4871949 [patent_doc_number] => 20080198683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/073847 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3898 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20080198683.pdf [firstpage_image] =>[orig_patent_app_number] => 12073847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 342511 [patent_doc_number] => 07502269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Semiconductor memory device capable of controlling drivability of overdriver' [patent_app_type] => utility [patent_app_number] => 12/073738 [patent_app_country] => US [patent_app_date] => 2008-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2873 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502269.pdf [firstpage_image] =>[orig_patent_app_number] => 12073738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4878255 [patent_doc_number] => 20080151638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'SELECTIVE THRESHOLD VOLTAGE VERIFICATION AND COMPACTION' [patent_app_type] => utility [patent_app_number] => 12/042021 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151638.pdf [firstpage_image] =>[orig_patent_app_number] => 12042021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4673928 [patent_doc_number] => 20080211556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/027411 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7006 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211556.pdf [firstpage_image] =>[orig_patent_app_number] => 12027411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5526032 [patent_doc_number] => 20090196109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'RANK SELECT USING A GLOBAL SELECT PIN' [patent_app_type] => utility [patent_app_number] => 12/026693 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6244 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20090196109.pdf [firstpage_image] =>[orig_patent_app_number] => 12026693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4531704 [patent_doc_number] => 07952929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Source side asymmetrical precharge programming scheme' [patent_app_type] => utility [patent_app_number] => 12/026825 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11919 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952929.pdf [firstpage_image] =>[orig_patent_app_number] => 12026825 [rel_patent_id] =>[rel_patent_doc_number] =>)