Trong Q. Phan

Array ( [id] => 4645712 [patent_doc_number] => 08023323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Non-volatile memory device having monitoring memory cell and related method of driving using variable read voltage' [patent_app_type] => utility [patent_app_number] => 12/023239 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6222 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/023/08023323.pdf [firstpage_image] =>[orig_patent_app_number] => 12023239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4878242 [patent_doc_number] => 20080151625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE ALLOWING EFFICIENT PROGRAMMING OPERATION AND ERASING OPERATION IN SHORT PERIOD OF TIME' [patent_app_type] => utility [patent_app_number] => 12/020958 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 17741 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151625.pdf [firstpage_image] =>[orig_patent_app_number] => 12020958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500785 [patent_doc_number] => 07957186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Non-volatile memory system and data read method of non-volatile memory system' [patent_app_type] => utility [patent_app_number] => 12/018300 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2820 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/957/07957186.pdf [firstpage_image] =>[orig_patent_app_number] => 12018300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8019783 [patent_doc_number] => 08139400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Enhanced static random access memory stability using asymmetric access transistors and design structure for same' [patent_app_type] => utility [patent_app_number] => 12/017404 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4275 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/139/08139400.pdf [firstpage_image] =>[orig_patent_app_number] => 12017404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5354066 [patent_doc_number] => 20090185410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER TUNNELING MAGNETIC MEMORIES UTILIZING UNIDIRECTIONAL POLARITY SELECTION DEVICES' [patent_app_type] => utility [patent_app_number] => 12/017532 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5773 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20090185410.pdf [firstpage_image] =>[orig_patent_app_number] => 12017532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4674740 [patent_doc_number] => 20080212368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'DATA VERIFICATION METHOD AND SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/017412 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3287 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20080212368.pdf [firstpage_image] =>[orig_patent_app_number] => 12017412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4831819 [patent_doc_number] => 20080130365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'BITLINE SELECTION CIRCUITRY FOR NONVOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 12/017297 [patent_app_country] => US [patent_app_date] => 2008-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2828 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20080130365.pdf [firstpage_image] =>[orig_patent_app_number] => 12017297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4876524 [patent_doc_number] => 20080149907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Complementary Resistive Memory Structure' [patent_app_type] => utility [patent_app_number] => 11/969985 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3139 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20080149907.pdf [firstpage_image] =>[orig_patent_app_number] => 11969985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4605594 [patent_doc_number] => 07986577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Precharge voltage supplying circuit' [patent_app_type] => utility [patent_app_number] => 12/005706 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2214 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986577.pdf [firstpage_image] =>[orig_patent_app_number] => 12005706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4630580 [patent_doc_number] => 08009485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/005932 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2867 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/009/08009485.pdf [firstpage_image] =>[orig_patent_app_number] => 12005932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15981 [patent_doc_number] => 07808805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Column address control circuit capable of selectively enabling sense amplifier in response to column addresses' [patent_app_type] => utility [patent_app_number] => 12/005494 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3399 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808805.pdf [firstpage_image] =>[orig_patent_app_number] => 12005494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5321711 [patent_doc_number] => 20090059701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Core voltage discharger and semiconductor memory device with the same' [patent_app_type] => utility [patent_app_number] => 12/005506 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3930 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059701.pdf [firstpage_image] =>[orig_patent_app_number] => 12005506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4763828 [patent_doc_number] => 20080175039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Memory cell provided with dual-gate transistors, with independent asymmetric gates' [patent_app_type] => utility [patent_app_number] => 12/005666 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9788 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175039.pdf [firstpage_image] =>[orig_patent_app_number] => 12005666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4438720 [patent_doc_number] => 07898851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Semiconductor memory device which includes memory cell having charge accumulation layer and control gate' [patent_app_type] => utility [patent_app_number] => 11/960158 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 12322 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898851.pdf [firstpage_image] =>[orig_patent_app_number] => 11960158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 85759 [patent_doc_number] => 07742325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Swapped-body RAM architecture' [patent_app_type] => utility [patent_app_number] => 11/958032 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5312 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/742/07742325.pdf [firstpage_image] =>[orig_patent_app_number] => 11958032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4544277 [patent_doc_number] => 07889536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Integrated circuit including quench devices' [patent_app_type] => utility [patent_app_number] => 11/957878 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6017 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889536.pdf [firstpage_image] =>[orig_patent_app_number] => 11957878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5544350 [patent_doc_number] => 20090154227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 11/957964 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9556 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20090154227.pdf [firstpage_image] =>[orig_patent_app_number] => 11957964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 104599 [patent_doc_number] => 07729173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Method for testing internal high voltage in nonvolatile semiconductor memory device and related voltage output circuit' [patent_app_type] => utility [patent_app_number] => 11/957808 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4225 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/729/07729173.pdf [firstpage_image] =>[orig_patent_app_number] => 11957808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4878218 [patent_doc_number] => 20080151601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'CIRCUITS AND METHODS FOR ADAPTIVE WRITE BIAS DRIVING OF RESISTIVE NON-VOLATILE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 11/957756 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7228 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20080151601.pdf [firstpage_image] =>[orig_patent_app_number] => 11957756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4480804 [patent_doc_number] => 07869256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto' [patent_app_type] => utility [patent_app_number] => 11/957812 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3377 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/869/07869256.pdf [firstpage_image] =>[orig_patent_app_number] => 11957812 [rel_patent_id] =>[rel_patent_doc_number] =>)