Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 115528 [patent_doc_number] => 07715224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'MRAM with enhanced programming margin' [patent_app_type] => utility [patent_app_number] => 11/787330 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 3919 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/715/07715224.pdf [firstpage_image] =>[orig_patent_app_number] => 11787330 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/787330
MRAM with enhanced programming margin Apr 15, 2007 Issued
Array ( [id] => 5246305 [patent_doc_number] => 20070242539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/783956 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11403 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242539.pdf [firstpage_image] =>[orig_patent_app_number] => 11783956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783956
Semiconductor memory device Apr 12, 2007 Issued
Array ( [id] => 5209375 [patent_doc_number] => 20070247959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/785006 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9661 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247959.pdf [firstpage_image] =>[orig_patent_app_number] => 11785006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785006
Semiconductor memory device Apr 12, 2007 Abandoned
Array ( [id] => 5164405 [patent_doc_number] => 20070285989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Column decoding system for semiconductor memory devices implemented with low voltage transistors' [patent_app_type] => utility [patent_app_number] => 11/787220 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6054 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285989.pdf [firstpage_image] =>[orig_patent_app_number] => 11787220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/787220
Column decoding system for semiconductor memory devices implemented with low voltage transistors Apr 11, 2007 Abandoned
Array ( [id] => 5246313 [patent_doc_number] => 20070242547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Self refresh operation of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/786594 [patent_app_country] => US [patent_app_date] => 2007-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5875 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242547.pdf [firstpage_image] =>[orig_patent_app_number] => 11786594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786594
Self refresh operation of semiconductor memory device Apr 11, 2007 Issued
Array ( [id] => 125529 [patent_doc_number] => 07706185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Reading circuitry in memory' [patent_app_type] => utility [patent_app_number] => 11/783334 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2685 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706185.pdf [firstpage_image] =>[orig_patent_app_number] => 11783334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783334
Reading circuitry in memory Apr 8, 2007 Issued
Array ( [id] => 4770386 [patent_doc_number] => 20080056044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Semiconductor device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/783318 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14845 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20080056044.pdf [firstpage_image] =>[orig_patent_app_number] => 11783318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783318
Semiconductor device and fabrication method thereof Apr 8, 2007 Issued
Array ( [id] => 367507 [patent_doc_number] => 07480192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-20 [patent_title] => 'Pull-up voltage circuit' [patent_app_type] => utility [patent_app_number] => 11/784290 [patent_app_country] => US [patent_app_date] => 2007-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5390 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480192.pdf [firstpage_image] =>[orig_patent_app_number] => 11784290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/784290
Pull-up voltage circuit Apr 5, 2007 Issued
Array ( [id] => 5186081 [patent_doc_number] => 20070164388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'MEMORY CELL COMPRISING A DIODE FABRICATED IN A LOW RESISTIVITY, PROGRAMMED STATE' [patent_app_type] => utility [patent_app_number] => 11/693858 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8182 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164388.pdf [firstpage_image] =>[orig_patent_app_number] => 11693858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693858
MEMORY CELL COMPRISING A DIODE FABRICATED IN A LOW RESISTIVITY, PROGRAMMED STATE Mar 29, 2007 Abandoned
Array ( [id] => 798571 [patent_doc_number] => 07428164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/717629 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 8698 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/428/07428164.pdf [firstpage_image] =>[orig_patent_app_number] => 11717629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717629
Semiconductor memory device Mar 13, 2007 Issued
Array ( [id] => 134050 [patent_doc_number] => 07701762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'NAND memory device and programming methods' [patent_app_type] => utility [patent_app_number] => 11/714542 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2427 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701762.pdf [firstpage_image] =>[orig_patent_app_number] => 11714542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714542
NAND memory device and programming methods Mar 5, 2007 Issued
Array ( [id] => 897792 [patent_doc_number] => 07342826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/713039 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 12541 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342826.pdf [firstpage_image] =>[orig_patent_app_number] => 11713039 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/713039
Semiconductor device Mar 1, 2007 Issued
Array ( [id] => 854795 [patent_doc_number] => 07379378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Over driving control signal generator in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/712466 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3769 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/379/07379378.pdf [firstpage_image] =>[orig_patent_app_number] => 11712466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/712466
Over driving control signal generator in semiconductor memory device Feb 28, 2007 Issued
Array ( [id] => 818319 [patent_doc_number] => 07411803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'Resistive coupled hall effect sensor' [patent_app_type] => utility [patent_app_number] => 11/679342 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5641 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411803.pdf [firstpage_image] =>[orig_patent_app_number] => 11679342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679342
Resistive coupled hall effect sensor Feb 26, 2007 Issued
Array ( [id] => 5003719 [patent_doc_number] => 20070201286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'INPUT CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/678480 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6048 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201286.pdf [firstpage_image] =>[orig_patent_app_number] => 11678480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678480
INPUT CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME Feb 22, 2007 Abandoned
Array ( [id] => 4725581 [patent_doc_number] => 20080205122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'MRAM MEMORY CONDITIONING' [patent_app_type] => utility [patent_app_number] => 11/678346 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4348 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205122.pdf [firstpage_image] =>[orig_patent_app_number] => 11678346 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678346
MRAM Memory conditioning Feb 22, 2007 Issued
Array ( [id] => 4725635 [patent_doc_number] => 20080205176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'MEMORY HAVING A DUMMY BITLINE FOR TIMING CONTROL' [patent_app_type] => utility [patent_app_number] => 11/677808 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7655 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205176.pdf [firstpage_image] =>[orig_patent_app_number] => 11677808 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677808
Memory having a dummy bitline for timing control Feb 21, 2007 Issued
Array ( [id] => 5003733 [patent_doc_number] => 20070201300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'SIGNAL SAMPLING APPARATUS AND METHOD FOR DRAM MEMORY' [patent_app_type] => utility [patent_app_number] => 11/675572 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2941 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201300.pdf [firstpage_image] =>[orig_patent_app_number] => 11675572 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675572
Signal sampling apparatus and method for DRAM memory Feb 14, 2007 Issued
Array ( [id] => 4766732 [patent_doc_number] => 20080177944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY' [patent_app_type] => utility [patent_app_number] => 11/675440 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2353 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20080177944.pdf [firstpage_image] =>[orig_patent_app_number] => 11675440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675440
Butterfly match-line structure and search method implemented thereby Feb 14, 2007 Issued
Array ( [id] => 315849 [patent_doc_number] => 07525827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Stored don\'t-care based hierarchical search-line scheme' [patent_app_type] => utility [patent_app_number] => 11/675386 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2423 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525827.pdf [firstpage_image] =>[orig_patent_app_number] => 11675386 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675386
Stored don't-care based hierarchical search-line scheme Feb 14, 2007 Issued
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