Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5676579 [patent_doc_number] => 20060181934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Methods for preventing fixed pattern programming' [patent_app_type] => utility [patent_app_number] => 11/335316 [patent_app_country] => US [patent_app_date] => 2006-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2111 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20060181934.pdf [firstpage_image] =>[orig_patent_app_number] => 11335316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335316
Methods for preventing fixed pattern programming Jan 18, 2006 Abandoned
Array ( [id] => 547221 [patent_doc_number] => 07177175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Low power programming technique for a floating body memory transistor, memory cell, and memory array' [patent_app_type] => utility [patent_app_number] => 11/334338 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7427 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177175.pdf [firstpage_image] =>[orig_patent_app_number] => 11334338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/334338
Low power programming technique for a floating body memory transistor, memory cell, and memory array Jan 16, 2006 Issued
Array ( [id] => 919770 [patent_doc_number] => 07324404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Clock control circuit for reducing consumption current in data input and output operations and semiconductor memory device including the same and data input and output operations methods of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/319578 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5552 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/324/07324404.pdf [firstpage_image] =>[orig_patent_app_number] => 11319578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/319578
Clock control circuit for reducing consumption current in data input and output operations and semiconductor memory device including the same and data input and output operations methods of semiconductor memory device Dec 28, 2005 Issued
Array ( [id] => 5187157 [patent_doc_number] => 20070165465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'REPAIR I/O FUSE CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/306072 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2193 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165465.pdf [firstpage_image] =>[orig_patent_app_number] => 11306072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/306072
Repair I/O fuse circuit of semiconductor memory device Dec 14, 2005 Issued
Array ( [id] => 5812180 [patent_doc_number] => 20060083054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Methods of operating a magnetic random access memory device and related devices and structures' [patent_app_type] => utility [patent_app_number] => 11/284546 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8862 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083054.pdf [firstpage_image] =>[orig_patent_app_number] => 11284546 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284546
Methods of operating a magnetic random access memory device and related devices and structures Nov 21, 2005 Issued
Array ( [id] => 5775500 [patent_doc_number] => 20060104140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Semiconductor memory device and refresh method thereof' [patent_app_type] => utility [patent_app_number] => 11/272792 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4502 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20060104140.pdf [firstpage_image] =>[orig_patent_app_number] => 11272792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/272792
Semiconductor memory device and refresh method thereof Nov 14, 2005 Issued
Array ( [id] => 5775510 [patent_doc_number] => 20060104150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/271816 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5174 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20060104150.pdf [firstpage_image] =>[orig_patent_app_number] => 11271816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271816
Semiconductor memory device Nov 13, 2005 Abandoned
Array ( [id] => 5214875 [patent_doc_number] => 20070103955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells' [patent_app_type] => utility [patent_app_number] => 11/271024 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4539 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103955.pdf [firstpage_image] =>[orig_patent_app_number] => 11271024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271024
Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells Nov 9, 2005 Issued
Array ( [id] => 7715169 [patent_doc_number] => 08094493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control' [patent_app_type] => utility [patent_app_number] => 11/271300 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4067 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/094/08094493.pdf [firstpage_image] =>[orig_patent_app_number] => 11271300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271300
Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control Nov 9, 2005 Issued
Array ( [id] => 870835 [patent_doc_number] => 07366047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Method and apparatus for reducing standby current in a dynamic random access memory during self refresh' [patent_app_type] => utility [patent_app_number] => 11/270178 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 10927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366047.pdf [firstpage_image] =>[orig_patent_app_number] => 11270178 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270178
Method and apparatus for reducing standby current in a dynamic random access memory during self refresh Nov 8, 2005 Issued
Array ( [id] => 482257 [patent_doc_number] => 07224596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Apparatus and method for repairing semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/270184 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8916 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224596.pdf [firstpage_image] =>[orig_patent_app_number] => 11270184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270184
Apparatus and method for repairing semiconductor memory device Nov 8, 2005 Issued
Array ( [id] => 5214882 [patent_doc_number] => 20070103962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Programmable memory cell and operation method' [patent_app_type] => utility [patent_app_number] => 11/271550 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3460 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103962.pdf [firstpage_image] =>[orig_patent_app_number] => 11271550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271550
Programmable memory cell and operation method Nov 8, 2005 Issued
Array ( [id] => 581426 [patent_doc_number] => 07463507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Memory device with a plurality of memory cells, in particular PCM memory cells, and method for operating such a memory cell device' [patent_app_type] => utility [patent_app_number] => 11/269898 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 8093 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463507.pdf [firstpage_image] =>[orig_patent_app_number] => 11269898 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269898
Memory device with a plurality of memory cells, in particular PCM memory cells, and method for operating such a memory cell device Nov 8, 2005 Issued
Array ( [id] => 5147240 [patent_doc_number] => 20070047294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Oscillating-field assisted spin torque switching of a magnetic tunnel junction memory element' [patent_app_type] => utility [patent_app_number] => 11/271208 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5836 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047294.pdf [firstpage_image] =>[orig_patent_app_number] => 11271208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/271208
Oscillating-field assisted spin torque switching of a magnetic tunnel junction memory element Nov 8, 2005 Issued
Array ( [id] => 451279 [patent_doc_number] => 07251148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Matchline sense circuit and method' [patent_app_type] => utility [patent_app_number] => 11/269659 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8864 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/251/07251148.pdf [firstpage_image] =>[orig_patent_app_number] => 11269659 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269659
Matchline sense circuit and method Nov 8, 2005 Issued
Array ( [id] => 5214898 [patent_doc_number] => 20070103978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Memory with retargetable memory cell redundancy' [patent_app_type] => utility [patent_app_number] => 11/270410 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7488 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103978.pdf [firstpage_image] =>[orig_patent_app_number] => 11270410 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270410
Memory with retargetable memory cell redundancy Nov 7, 2005 Issued
Array ( [id] => 5214897 [patent_doc_number] => 20070103977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Retargetable memory cell redundancy methods' [patent_app_type] => utility [patent_app_number] => 11/270198 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7489 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103977.pdf [firstpage_image] =>[orig_patent_app_number] => 11270198 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270198
Retargetable memory cell redundancy methods Nov 7, 2005 Issued
Array ( [id] => 5825378 [patent_doc_number] => 20060062055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/268471 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7688 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20060062055.pdf [firstpage_image] =>[orig_patent_app_number] => 11268471 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268471
Semiconductor memory Nov 7, 2005 Issued
Array ( [id] => 437166 [patent_doc_number] => 07263015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Address decoding' [patent_app_type] => utility [patent_app_number] => 11/267574 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5352 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/263/07263015.pdf [firstpage_image] =>[orig_patent_app_number] => 11267574 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267574
Address decoding Nov 6, 2005 Issued
Array ( [id] => 5214881 [patent_doc_number] => 20070103961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'RAM cell with soft error protection using ferroelectric material' [patent_app_type] => utility [patent_app_number] => 11/268006 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2379 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103961.pdf [firstpage_image] =>[orig_patent_app_number] => 11268006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268006
RAM cell with soft error protection using ferroelectric material Nov 6, 2005 Abandoned
Menu