
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5676579
[patent_doc_number] => 20060181934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-17
[patent_title] => 'Methods for preventing fixed pattern programming'
[patent_app_type] => utility
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[patent_app_date] => 2006-01-19
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[pdf_file] => publications/A1/0181/20060181934.pdf
[firstpage_image] =>[orig_patent_app_number] => 11335316
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/335316 | Methods for preventing fixed pattern programming | Jan 18, 2006 | Abandoned |
Array
(
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[patent_doc_number] => 07177175
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[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Low power programming technique for a floating body memory transistor, memory cell, and memory array'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11334338
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/334338 | Low power programming technique for a floating body memory transistor, memory cell, and memory array | Jan 16, 2006 | Issued |
Array
(
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[patent_doc_number] => 07324404
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[patent_issue_date] => 2008-01-29
[patent_title] => 'Clock control circuit for reducing consumption current in data input and output operations and semiconductor memory device including the same and data input and output operations methods of semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/319578
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319578 | Clock control circuit for reducing consumption current in data input and output operations and semiconductor memory device including the same and data input and output operations methods of semiconductor memory device | Dec 28, 2005 | Issued |
Array
(
[id] => 5187157
[patent_doc_number] => 20070165465
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[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'REPAIR I/O FUSE CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/306072
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/306072 | Repair I/O fuse circuit of semiconductor memory device | Dec 14, 2005 | Issued |
Array
(
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[patent_issue_date] => 2006-04-20
[patent_title] => 'Methods of operating a magnetic random access memory device and related devices and structures'
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[patent_app_number] => 11/284546
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[patent_app_date] => 2005-11-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/284546 | Methods of operating a magnetic random access memory device and related devices and structures | Nov 21, 2005 | Issued |
Array
(
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[patent_title] => 'Semiconductor memory device and refresh method thereof'
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Array
(
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[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/271816
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11271816
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/271816 | Semiconductor memory device | Nov 13, 2005 | Abandoned |
Array
(
[id] => 5214875
[patent_doc_number] => 20070103955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/271024
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[firstpage_image] =>[orig_patent_app_number] => 11271024
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/271024 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells | Nov 9, 2005 | Issued |
Array
(
[id] => 7715169
[patent_doc_number] => 08094493
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[patent_kind] => B2
[patent_issue_date] => 2012-01-10
[patent_title] => 'Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control'
[patent_app_type] => utility
[patent_app_number] => 11/271300
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/271300 | Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control | Nov 9, 2005 | Issued |
Array
(
[id] => 870835
[patent_doc_number] => 07366047
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[patent_title] => 'Method and apparatus for reducing standby current in a dynamic random access memory during self refresh'
[patent_app_type] => utility
[patent_app_number] => 11/270178
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/270178 | Method and apparatus for reducing standby current in a dynamic random access memory during self refresh | Nov 8, 2005 | Issued |
Array
(
[id] => 482257
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[patent_title] => 'Apparatus and method for repairing semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/270184 | Apparatus and method for repairing semiconductor memory device | Nov 8, 2005 | Issued |
Array
(
[id] => 5214882
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[patent_title] => 'Programmable memory cell and operation method'
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Array
(
[id] => 581426
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[patent_title] => 'Memory device with a plurality of memory cells, in particular PCM memory cells, and method for operating such a memory cell device'
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Array
(
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[patent_title] => 'Oscillating-field assisted spin torque switching of a magnetic tunnel junction memory element'
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[patent_app_number] => 11/271208
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Array
(
[id] => 451279
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[patent_title] => 'Matchline sense circuit and method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/269659 | Matchline sense circuit and method | Nov 8, 2005 | Issued |
Array
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/268006 | RAM cell with soft error protection using ferroelectric material | Nov 6, 2005 | Abandoned |