Trong Q. Phan

Array ( [id] => 5746796 [patent_doc_number] => 20060109727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Integrated semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/267572 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6690 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109727.pdf [firstpage_image] =>[orig_patent_app_number] => 11267572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 282841 [patent_doc_number] => 07554843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'Serial bus incorporating high voltage programming signals' [patent_app_type] => utility [patent_app_number] => 11/267460 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3418 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554843.pdf [firstpage_image] =>[orig_patent_app_number] => 11267460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 308456 [patent_doc_number] => 07532534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Voltage generating circuit and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 11/267844 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6194 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/532/07532534.pdf [firstpage_image] =>[orig_patent_app_number] => 11267844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5825341 [patent_doc_number] => 20060062044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Methods of operating magnetic random access memory devices including heat-generating structures' [patent_app_type] => utility [patent_app_number] => 11/263521 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10261 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20060062044.pdf [firstpage_image] =>[orig_patent_app_number] => 11263521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 842132 [patent_doc_number] => 07391648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Low voltage sense amplifier for operation under a reduced bit line bias voltage' [patent_app_type] => utility [patent_app_number] => 11/260597 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3906 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391648.pdf [firstpage_image] =>[orig_patent_app_number] => 11260597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5451190 [patent_doc_number] => 20090067226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'INTEGRATED CIRCUIT WITH PHASE-CHANGE MEMORY CELLS AND METHOD FOR ADDRESSING PHASE-CHANGE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 11/577708 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4471 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20090067226.pdf [firstpage_image] =>[orig_patent_app_number] => 11577708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 610304 [patent_doc_number] => 07151690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-19 [patent_title] => '6F2 3-Transistor DRAM gain cell' [patent_app_type] => utility [patent_app_number] => 11/245765 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5297 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151690.pdf [firstpage_image] =>[orig_patent_app_number] => 11245765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5665848 [patent_doc_number] => 20060171198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Spin-injection magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 11/242906 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20060171198.pdf [firstpage_image] =>[orig_patent_app_number] => 11242906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5746386 [patent_doc_number] => 20060109316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Storage and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/243342 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7833 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109316.pdf [firstpage_image] =>[orig_patent_app_number] => 11243342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 487005 [patent_doc_number] => 07221615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Semiconductor memory chip' [patent_app_type] => utility [patent_app_number] => 11/242150 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4604 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221615.pdf [firstpage_image] =>[orig_patent_app_number] => 11242150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5812218 [patent_doc_number] => 20060083091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Semiconductor storage device precharging/discharging bit line to read data from memory cell' [patent_app_type] => utility [patent_app_number] => 11/240620 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 36518 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083091.pdf [firstpage_image] =>[orig_patent_app_number] => 11240620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 490114 [patent_doc_number] => 07218555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Imaging cell that has a long integration period and method of operating the imaging cell' [patent_app_type] => utility [patent_app_number] => 11/242094 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6116 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218555.pdf [firstpage_image] =>[orig_patent_app_number] => 11242094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5134883 [patent_doc_number] => 20070076512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Three transistor wordline decoder' [patent_app_type] => utility [patent_app_number] => 11/241324 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2116 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20070076512.pdf [firstpage_image] =>[orig_patent_app_number] => 11241324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 419629 [patent_doc_number] => 07277307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-02 [patent_title] => 'Column defect detection in a content addressable memory' [patent_app_type] => utility [patent_app_number] => 11/240160 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8055 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/277/07277307.pdf [firstpage_image] =>[orig_patent_app_number] => 11240160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 827752 [patent_doc_number] => 07403418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Word line voltage boosting circuit and a memory array incorporating same' [patent_app_type] => utility [patent_app_number] => 11/241582 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3831 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/403/07403418.pdf [firstpage_image] =>[orig_patent_app_number] => 11241582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 377917 [patent_doc_number] => 07313021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Nonvolatile memory circuit' [patent_app_type] => utility [patent_app_number] => 11/239802 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6596 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313021.pdf [firstpage_image] =>[orig_patent_app_number] => 11239802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5170250 [patent_doc_number] => 20070070681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Memory device comprising an array of resistive memory cells' [patent_app_type] => utility [patent_app_number] => 11/238116 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5112 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070681.pdf [firstpage_image] =>[orig_patent_app_number] => 11238116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 409875 [patent_doc_number] => 07286380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Reconfigurable memory block redundancy to repair defective input/output lines' [patent_app_type] => utility [patent_app_number] => 11/240304 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286380.pdf [firstpage_image] =>[orig_patent_app_number] => 11240304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5170323 [patent_doc_number] => 20070070754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Low equalized sense-amp for twin cell DRAMs' [patent_app_type] => utility [patent_app_number] => 11/241592 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5274 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070754.pdf [firstpage_image] =>[orig_patent_app_number] => 11241592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5038143 [patent_doc_number] => 20070090425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Memory cell comprising switchable semiconductor memory element with trimmable resistance' [patent_app_type] => utility [patent_app_number] => 11/237167 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090425.pdf [firstpage_image] =>[orig_patent_app_number] => 11237167 [rel_patent_id] =>[rel_patent_doc_number] =>)