Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 827820 [patent_doc_number] => 07403446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-22 [patent_title] => 'Single late-write for standard synchronous SRAMs' [patent_app_type] => utility [patent_app_number] => 11/237378 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4024 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/403/07403446.pdf [firstpage_image] =>[orig_patent_app_number] => 11237378 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/237378
Single late-write for standard synchronous SRAMs Sep 26, 2005 Issued
Array ( [id] => 433628 [patent_doc_number] => 07266021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-04 [patent_title] => 'Latch-based random access memory (LBRAM) tri-state banking architecture' [patent_app_type] => utility [patent_app_number] => 11/237064 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266021.pdf [firstpage_image] =>[orig_patent_app_number] => 11237064 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/237064
Latch-based random access memory (LBRAM) tri-state banking architecture Sep 26, 2005 Issued
Array ( [id] => 5269977 [patent_doc_number] => 20090073753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/915126 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10587 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20090073753.pdf [firstpage_image] =>[orig_patent_app_number] => 11915126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/915126
Semiconductor device Sep 20, 2005 Issued
Array ( [id] => 858769 [patent_doc_number] => 07376006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element' [patent_app_type] => utility [patent_app_number] => 11/216518 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4658 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376006.pdf [firstpage_image] =>[orig_patent_app_number] => 11216518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216518
Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element Aug 30, 2005 Issued
Array ( [id] => 5147257 [patent_doc_number] => 20070047311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Selective threshold voltage verification and compaction' [patent_app_type] => utility [patent_app_number] => 11/216742 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5752 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 30 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047311.pdf [firstpage_image] =>[orig_patent_app_number] => 11216742 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216742
Selective threshold voltage verification and compaction Aug 30, 2005 Issued
Array ( [id] => 5147273 [patent_doc_number] => 20070047327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Erase method for flash memory' [patent_app_type] => utility [patent_app_number] => 11/215940 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9012 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047327.pdf [firstpage_image] =>[orig_patent_app_number] => 11215940 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215940
Erase method for flash memory Aug 30, 2005 Abandoned
Array ( [id] => 76582 [patent_doc_number] => 07751242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'NAND memory device and programming methods' [patent_app_type] => utility [patent_app_number] => 11/215990 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2563 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/751/07751242.pdf [firstpage_image] =>[orig_patent_app_number] => 11215990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215990
NAND memory device and programming methods Aug 29, 2005 Issued
Array ( [id] => 5725495 [patent_doc_number] => 20060056255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Semiconductor memory apparatus and method for operating a semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 11/215640 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3264 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20060056255.pdf [firstpage_image] =>[orig_patent_app_number] => 11215640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215640
Semiconductor memory apparatus and method for operating a semiconductor memory apparatus Aug 29, 2005 Abandoned
Array ( [id] => 5147253 [patent_doc_number] => 20070047307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'High speed operation method for twin MONOS metal bit array' [patent_app_type] => utility [patent_app_number] => 11/215418 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 6729 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047307.pdf [firstpage_image] =>[orig_patent_app_number] => 11215418 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215418
High speed operation method for twin MONOS metal bit array Aug 29, 2005 Issued
Array ( [id] => 419736 [patent_doc_number] => 07277355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Method and apparatus for generating temperature-compensated read and verify operations in flash memories' [patent_app_type] => utility [patent_app_number] => 11/215836 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 6433 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/277/07277355.pdf [firstpage_image] =>[orig_patent_app_number] => 11215836 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215836
Method and apparatus for generating temperature-compensated read and verify operations in flash memories Aug 28, 2005 Issued
Array ( [id] => 5709232 [patent_doc_number] => 20060050577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Memory module with programmable fuse element' [patent_app_type] => utility [patent_app_number] => 11/214276 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3522 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20060050577.pdf [firstpage_image] =>[orig_patent_app_number] => 11214276 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214276
Memory module with programmable fuse element Aug 28, 2005 Abandoned
Array ( [id] => 383924 [patent_doc_number] => 07307878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-11 [patent_title] => 'Flash memory device having improved program rate' [patent_app_type] => utility [patent_app_number] => 11/212850 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5015 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307878.pdf [firstpage_image] =>[orig_patent_app_number] => 11212850 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212850
Flash memory device having improved program rate Aug 28, 2005 Issued
Array ( [id] => 887745 [patent_doc_number] => 07352626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-01 [patent_title] => 'Voltage regulator with less overshoot and faster settling time' [patent_app_type] => utility [patent_app_number] => 11/212614 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4818 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352626.pdf [firstpage_image] =>[orig_patent_app_number] => 11212614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212614
Voltage regulator with less overshoot and faster settling time Aug 28, 2005 Issued
Array ( [id] => 5709201 [patent_doc_number] => 20060050546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Memory circuit having memory cells which have a resistance memory element' [patent_app_type] => utility [patent_app_number] => 11/213372 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7031 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20060050546.pdf [firstpage_image] =>[orig_patent_app_number] => 11213372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213372
Memory circuit having memory cells which have a resistance memory element Aug 25, 2005 Issued
Array ( [id] => 5147237 [patent_doc_number] => 20070047291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Integrated memory circuit comprising a resistive memory element and a method for manufacturing such a memory circuit' [patent_app_type] => utility [patent_app_number] => 11/213560 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5693 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047291.pdf [firstpage_image] =>[orig_patent_app_number] => 11213560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213560
Integrated memory circuit comprising a resistive memory element and a method for manufacturing such a memory circuit Aug 25, 2005 Abandoned
Array ( [id] => 6930076 [patent_doc_number] => 20050281110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/211543 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 9536 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20050281110.pdf [firstpage_image] =>[orig_patent_app_number] => 11211543 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211543
Semiconductor integrated circuit device Aug 25, 2005 Issued
Array ( [id] => 926331 [patent_doc_number] => 07317631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Method for reading Uniform Channel Program (UCP) flash memory cells' [patent_app_type] => utility [patent_app_number] => 11/213670 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3152 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/317/07317631.pdf [firstpage_image] =>[orig_patent_app_number] => 11213670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213670
Method for reading Uniform Channel Program (UCP) flash memory cells Aug 25, 2005 Issued
Array ( [id] => 5636156 [patent_doc_number] => 20060067129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Method for reading electrically programmable and erasable memory cells, with bit line precharge-ahead' [patent_app_type] => utility [patent_app_number] => 11/212480 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067129.pdf [firstpage_image] =>[orig_patent_app_number] => 11212480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212480
Method for reading electrically programmable and erasable memory cells, with bit line precharge-ahead Aug 24, 2005 Issued
Array ( [id] => 5147244 [patent_doc_number] => 20070047298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Method and apparatus for reducing operation disturbance' [patent_app_type] => utility [patent_app_number] => 11/212206 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3276 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047298.pdf [firstpage_image] =>[orig_patent_app_number] => 11212206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212206
Method and apparatus for reducing operation disturbance Aug 24, 2005 Issued
Array ( [id] => 883137 [patent_doc_number] => 07355915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Memory circuit with supply voltage flexibility and supply voltage adapted performance' [patent_app_type] => utility [patent_app_number] => 11/212082 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5612 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355915.pdf [firstpage_image] =>[orig_patent_app_number] => 11212082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212082
Memory circuit with supply voltage flexibility and supply voltage adapted performance Aug 23, 2005 Issued
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