Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7073693 [patent_doc_number] => 20050146960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/048915 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7408 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146960.pdf [firstpage_image] =>[orig_patent_app_number] => 11048915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048915
Semiconductor memory Feb 2, 2005 Issued
Array ( [id] => 678406 [patent_doc_number] => 07088619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method for programming and erasing an NROM cell' [patent_app_type] => utility [patent_app_number] => 11/047809 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088619.pdf [firstpage_image] =>[orig_patent_app_number] => 11047809 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/047809
Method for programming and erasing an NROM cell Jan 31, 2005 Issued
Array ( [id] => 786470 [patent_doc_number] => 06990021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Low voltage sense amplifier for operation under a reduced bit line bias voltage' [patent_app_type] => utility [patent_app_number] => 11/037915 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 8 [patent_no_of_words] => 3840 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990021.pdf [firstpage_image] =>[orig_patent_app_number] => 11037915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037915
Low voltage sense amplifier for operation under a reduced bit line bias voltage Jan 17, 2005 Issued
Array ( [id] => 7141759 [patent_doc_number] => 20050117427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Dense content addressable memory cell' [patent_app_type] => utility [patent_app_number] => 11/030810 [patent_app_country] => US [patent_app_date] => 2005-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2360 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20050117427.pdf [firstpage_image] =>[orig_patent_app_number] => 11030810 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030810
Dense content addressable memory cell Jan 6, 2005 Issued
Array ( [id] => 874838 [patent_doc_number] => 07362631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Semiconductor memory device capable of controlling drivability of overdriver' [patent_app_type] => utility [patent_app_number] => 11/019188 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2827 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362631.pdf [firstpage_image] =>[orig_patent_app_number] => 11019188 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019188
Semiconductor memory device capable of controlling drivability of overdriver Dec 22, 2004 Issued
Array ( [id] => 5654259 [patent_doc_number] => 20060139994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Method of programming, reading and erasing memory-diode in a memory-diode array' [patent_app_type] => utility [patent_app_number] => 11/021958 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5945 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139994.pdf [firstpage_image] =>[orig_patent_app_number] => 11021958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021958
Method of programming, reading and erasing memory-diode in a memory-diode array Dec 22, 2004 Issued
Array ( [id] => 6904477 [patent_doc_number] => 20050099872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Low-voltage sense amplifier and method' [patent_app_type] => utility [patent_app_number] => 11/015045 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4238 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20050099872.pdf [firstpage_image] =>[orig_patent_app_number] => 11015045 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015045
Low-voltage sense amplifier and method Dec 16, 2004 Issued
Array ( [id] => 7225690 [patent_doc_number] => 20050078504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Plateline driver with RAMP rate control' [patent_app_type] => utility [patent_app_number] => 11/003707 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4924 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20050078504.pdf [firstpage_image] =>[orig_patent_app_number] => 11003707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003707
Plateline driver with RAMP rate control Dec 2, 2004 Issued
Array ( [id] => 7247412 [patent_doc_number] => 20050073894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Zero latency-zero bus turnaround synchronous flash memory' [patent_app_type] => utility [patent_app_number] => 11/000551 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 14136 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073894.pdf [firstpage_image] =>[orig_patent_app_number] => 11000551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000551
Zero latency-zero bus turnaround synchronous flash memory Nov 30, 2004 Abandoned
Array ( [id] => 786468 [patent_doc_number] => 06990020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Non-volatile memory cell techniques' [patent_app_type] => utility [patent_app_number] => 10/984077 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990020.pdf [firstpage_image] =>[orig_patent_app_number] => 10984077 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/984077
Non-volatile memory cell techniques Nov 7, 2004 Issued
Array ( [id] => 718887 [patent_doc_number] => 07054193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Non-uniform programming pulse width for writing of multi-bit-per-cell memories' [patent_app_type] => utility [patent_app_number] => 10/982298 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 13773 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/054/07054193.pdf [firstpage_image] =>[orig_patent_app_number] => 10982298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982298
Non-uniform programming pulse width for writing of multi-bit-per-cell memories Nov 4, 2004 Issued
Array ( [id] => 7204489 [patent_doc_number] => 20050052930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Semiconductor memory device including page latch circuit' [patent_app_type] => utility [patent_app_number] => 10/968303 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8711 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052930.pdf [firstpage_image] =>[orig_patent_app_number] => 10968303 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/968303
Semiconductor memory device including page latch circuit Oct 19, 2004 Issued
Array ( [id] => 526348 [patent_doc_number] => 07193922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/968072 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6104 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193922.pdf [firstpage_image] =>[orig_patent_app_number] => 10968072 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/968072
Semiconductor integrated circuit Oct 19, 2004 Issued
Array ( [id] => 7009509 [patent_doc_number] => 20050063225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Semiconductor memory device and various systems mounting them' [patent_app_type] => utility [patent_app_number] => 10/963820 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 219 [patent_figures_cnt] => 219 [patent_no_of_words] => 66991 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20050063225.pdf [firstpage_image] =>[orig_patent_app_number] => 10963820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/963820
Semiconductor memory device and various systems mounting them Oct 13, 2004 Issued
Array ( [id] => 723371 [patent_doc_number] => 07050318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Selective match line pre-charging in a CAM device using pre-compare operations' [patent_app_type] => utility [patent_app_number] => 10/957060 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 16843 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/050/07050318.pdf [firstpage_image] =>[orig_patent_app_number] => 10957060 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957060
Selective match line pre-charging in a CAM device using pre-compare operations Sep 30, 2004 Issued
Array ( [id] => 5819240 [patent_doc_number] => 20060023553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Semiconductor device having hierarchized bit lines' [patent_app_type] => utility [patent_app_number] => 10/952824 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5505 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20060023553.pdf [firstpage_image] =>[orig_patent_app_number] => 10952824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952824
Semiconductor device having hierarchized bit lines Sep 29, 2004 Issued
Array ( [id] => 597417 [patent_doc_number] => 07436727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Method and apparatus to control a power consumption of a memory device' [patent_app_type] => utility [patent_app_number] => 10/956289 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3613 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/436/07436727.pdf [firstpage_image] =>[orig_patent_app_number] => 10956289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956289
Method and apparatus to control a power consumption of a memory device Sep 29, 2004 Issued
Array ( [id] => 297045 [patent_doc_number] => 07542322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Buffered continuous multi-drop clock ring' [patent_app_type] => utility [patent_app_number] => 10/956397 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1694 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/542/07542322.pdf [firstpage_image] =>[orig_patent_app_number] => 10956397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956397
Buffered continuous multi-drop clock ring Sep 29, 2004 Issued
Array ( [id] => 5636125 [patent_doc_number] => 20060067098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Content addressable memory cell including resistive memory elements' [patent_app_type] => utility [patent_app_number] => 10/955836 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2482 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067098.pdf [firstpage_image] =>[orig_patent_app_number] => 10955836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/955836
Content addressable memory cell including resistive memory elements Sep 29, 2004 Issued
Array ( [id] => 697628 [patent_doc_number] => 07072214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'NOR flash memory device and method of shortening a program time' [patent_app_type] => utility [patent_app_number] => 10/957182 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3937 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/072/07072214.pdf [firstpage_image] =>[orig_patent_app_number] => 10957182 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957182
NOR flash memory device and method of shortening a program time Sep 29, 2004 Issued
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