Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 652195 [patent_doc_number] => 07113417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Integrated memory circuit' [patent_app_type] => utility [patent_app_number] => 10/954596 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6704 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/113/07113417.pdf [firstpage_image] =>[orig_patent_app_number] => 10954596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954596
Integrated memory circuit Sep 29, 2004 Issued
Array ( [id] => 7102627 [patent_doc_number] => 20050105353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method for operating a memory cell array' [patent_app_type] => utility [patent_app_number] => 10/954642 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20050105353.pdf [firstpage_image] =>[orig_patent_app_number] => 10954642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954642
Method for operating a memory cell array Sep 29, 2004 Issued
Array ( [id] => 902519 [patent_doc_number] => 07339813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Complementary output resistive memory cell' [patent_app_type] => utility [patent_app_number] => 10/957298 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3079 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/339/07339813.pdf [firstpage_image] =>[orig_patent_app_number] => 10957298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957298
Complementary output resistive memory cell Sep 29, 2004 Issued
Array ( [id] => 701685 [patent_doc_number] => 07068533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Resistive memory cell configuration and method for sensing resistance values' [patent_app_type] => utility [patent_app_number] => 10/955832 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068533.pdf [firstpage_image] =>[orig_patent_app_number] => 10955832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/955832
Resistive memory cell configuration and method for sensing resistance values Sep 29, 2004 Issued
Array ( [id] => 5636144 [patent_doc_number] => 20060067117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Fuse memory cell comprising a diode, the diode serving as the fuse element' [patent_app_type] => utility [patent_app_number] => 10/955387 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7257 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067117.pdf [firstpage_image] =>[orig_patent_app_number] => 10955387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/955387
Fuse memory cell comprising a diode, the diode serving as the fuse element Sep 28, 2004 Abandoned
Array ( [id] => 467045 [patent_doc_number] => 07239565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Memory array with precharge control circuit' [patent_app_type] => utility [patent_app_number] => 10/954250 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6912 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239565.pdf [firstpage_image] =>[orig_patent_app_number] => 10954250 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954250
Memory array with precharge control circuit Sep 28, 2004 Issued
Array ( [id] => 543130 [patent_doc_number] => 07180808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Semiconductor memory device for performing refresh operation' [patent_app_type] => utility [patent_app_number] => 10/954530 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2280 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180808.pdf [firstpage_image] =>[orig_patent_app_number] => 10954530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/954530
Semiconductor memory device for performing refresh operation Sep 28, 2004 Issued
Array ( [id] => 5636163 [patent_doc_number] => 20060067136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Low leakage and leakage tolerant stack free multi-ported register file' [patent_app_type] => utility [patent_app_number] => 10/953202 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4619 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067136.pdf [firstpage_image] =>[orig_patent_app_number] => 10953202 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/953202
Low leakage and leakage tolerant stack free multi-ported register file Sep 27, 2004 Issued
Array ( [id] => 689033 [patent_doc_number] => 07079426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Dynamic multi-Vcc scheme for SRAM cell stability control' [patent_app_type] => utility [patent_app_number] => 10/950740 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/079/07079426.pdf [firstpage_image] =>[orig_patent_app_number] => 10950740 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950740
Dynamic multi-Vcc scheme for SRAM cell stability control Sep 26, 2004 Issued
Array ( [id] => 545388 [patent_doc_number] => 07173875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'SRAM array with improved cell stability' [patent_app_type] => utility [patent_app_number] => 10/950928 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3993 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173875.pdf [firstpage_image] =>[orig_patent_app_number] => 10950928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950928
SRAM array with improved cell stability Sep 26, 2004 Issued
Array ( [id] => 399200 [patent_doc_number] => 07295457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Integrated circuit chip with improved array stability' [patent_app_type] => utility [patent_app_number] => 10/950940 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3474 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295457.pdf [firstpage_image] =>[orig_patent_app_number] => 10950940 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950940
Integrated circuit chip with improved array stability Sep 26, 2004 Issued
Array ( [id] => 5636124 [patent_doc_number] => 20060067097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Binary and ternary non-volatile CAM' [patent_app_type] => utility [patent_app_number] => 10/950186 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7474 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067097.pdf [firstpage_image] =>[orig_patent_app_number] => 10950186 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950186
Binary and ternary non-volatile CAM Sep 23, 2004 Issued
Array ( [id] => 6970676 [patent_doc_number] => 20050036386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Method and apparatus for synchronization of row and column access operations' [patent_app_type] => utility [patent_app_number] => 10/946016 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3808 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20050036386.pdf [firstpage_image] =>[orig_patent_app_number] => 10946016 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/946016
Method and apparatus for synchronization of row and column access operations Sep 21, 2004 Issued
Array ( [id] => 684207 [patent_doc_number] => 07082065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Method and apparatus for efficient utilization of electronic fuse source connections' [patent_app_type] => utility [patent_app_number] => 10/711430 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4142 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082065.pdf [firstpage_image] =>[orig_patent_app_number] => 10711430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711430
Method and apparatus for efficient utilization of electronic fuse source connections Sep 16, 2004 Issued
Array ( [id] => 7126219 [patent_doc_number] => 20050057963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Semiconductor memory device having memory block configuration' [patent_app_type] => utility [patent_app_number] => 10/940764 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11170 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057963.pdf [firstpage_image] =>[orig_patent_app_number] => 10940764 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/940764
Semiconductor memory device having memory block configuration Sep 14, 2004 Issued
Array ( [id] => 7126226 [patent_doc_number] => 20050057970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Nonvolatile memory device includng circuit formed of thin film transistors' [patent_app_type] => utility [patent_app_number] => 10/941102 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12434 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057970.pdf [firstpage_image] =>[orig_patent_app_number] => 10941102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/941102
Nonvolatile memory device including circuit formed of thin film transistors Sep 14, 2004 Issued
Array ( [id] => 547974 [patent_doc_number] => 07177229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Apparatus for tuning a RAS active time in a memory device' [patent_app_type] => utility [patent_app_number] => 10/941804 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4074 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177229.pdf [firstpage_image] =>[orig_patent_app_number] => 10941804 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/941804
Apparatus for tuning a RAS active time in a memory device Sep 14, 2004 Issued
Array ( [id] => 7009527 [patent_doc_number] => 20050063243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Decoding circuit for memory device' [patent_app_type] => utility [patent_app_number] => 10/941552 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2799 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20050063243.pdf [firstpage_image] =>[orig_patent_app_number] => 10941552 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/941552
Decoding circuit for memory device Sep 14, 2004 Issued
Array ( [id] => 475525 [patent_doc_number] => 07230852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time' [patent_app_type] => utility [patent_app_number] => 10/940812 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 47 [patent_no_of_words] => 17666 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230852.pdf [firstpage_image] =>[orig_patent_app_number] => 10940812 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/940812
Non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in short period of time Sep 14, 2004 Issued
Array ( [id] => 784583 [patent_doc_number] => 06992949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Method and circuit for controlling generation of column selection line signal' [patent_app_type] => utility [patent_app_number] => 10/941446 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5100 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992949.pdf [firstpage_image] =>[orig_patent_app_number] => 10941446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/941446
Method and circuit for controlling generation of column selection line signal Sep 14, 2004 Issued
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