Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 959423 [patent_doc_number] => 06954371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/860770 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 9535 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954371.pdf [firstpage_image] =>[orig_patent_app_number] => 10860770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/860770
Semiconductor integrated circuit device Jun 3, 2004 Issued
Array ( [id] => 954527 [patent_doc_number] => 06958944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-25 [patent_title] => 'Enhanced refresh circuit and method for reduction of DRAM refresh cycles' [patent_app_type] => utility [patent_app_number] => 10/854051 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958944.pdf [firstpage_image] =>[orig_patent_app_number] => 10854051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854051
Enhanced refresh circuit and method for reduction of DRAM refresh cycles May 25, 2004 Issued
Array ( [id] => 969845 [patent_doc_number] => 06940747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-06 [patent_title] => 'Magnetic memory device' [patent_app_type] => utility [patent_app_number] => 10/854858 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3161 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940747.pdf [firstpage_image] =>[orig_patent_app_number] => 10854858 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854858
Magnetic memory device May 25, 2004 Issued
Array ( [id] => 486999 [patent_doc_number] => 07221613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Memory with serial input/output terminals for address and data and method therefor' [patent_app_type] => utility [patent_app_number] => 10/854554 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6476 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221613.pdf [firstpage_image] =>[orig_patent_app_number] => 10854554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854554
Memory with serial input/output terminals for address and data and method therefor May 25, 2004 Issued
Array ( [id] => 1029524 [patent_doc_number] => 06882572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges' [patent_app_type] => utility [patent_app_number] => 10/849975 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 102 [patent_no_of_words] => 14162 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882572.pdf [firstpage_image] =>[orig_patent_app_number] => 10849975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/849975
Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges May 18, 2004 Issued
Array ( [id] => 7059864 [patent_doc_number] => 20050002224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/845270 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002224.pdf [firstpage_image] =>[orig_patent_app_number] => 10845270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845270
Semiconductor integrated circuit device May 13, 2004 Issued
Array ( [id] => 7220393 [patent_doc_number] => 20050254285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Cache late select circuit' [patent_app_type] => utility [patent_app_number] => 10/844296 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2212 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20050254285.pdf [firstpage_image] =>[orig_patent_app_number] => 10844296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844296
Cache late select circuit May 11, 2004 Issued
Array ( [id] => 7044381 [patent_doc_number] => 20050248976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Dynamic random access memory cell leakage current detector' [patent_app_type] => utility [patent_app_number] => 10/840098 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3228 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20050248976.pdf [firstpage_image] =>[orig_patent_app_number] => 10840098 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840098
Dynamic random access memory cell leakage current detector May 5, 2004 Issued
Array ( [id] => 7059881 [patent_doc_number] => 20050002241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Memory system with improved signal integrity' [patent_app_type] => utility [patent_app_number] => 10/837610 [patent_app_country] => US [patent_app_date] => 2004-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2643 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002241.pdf [firstpage_image] =>[orig_patent_app_number] => 10837610 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/837610
Memory system with improved signal integrity May 3, 2004 Abandoned
Array ( [id] => 854775 [patent_doc_number] => 07379367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Memory controller and semiconductor comprising the same' [patent_app_type] => utility [patent_app_number] => 10/834757 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2031 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/379/07379367.pdf [firstpage_image] =>[orig_patent_app_number] => 10834757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834757
Memory controller and semiconductor comprising the same Apr 28, 2004 Issued
Array ( [id] => 718913 [patent_doc_number] => 07054204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Semiconductor device and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 10/828454 [patent_app_country] => US [patent_app_date] => 2004-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7267 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/054/07054204.pdf [firstpage_image] =>[orig_patent_app_number] => 10828454 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/828454
Semiconductor device and method for controlling the same Apr 19, 2004 Issued
Array ( [id] => 7293479 [patent_doc_number] => 20040213040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Magnetic random access memory device' [patent_app_type] => new [patent_app_number] => 10/828894 [patent_app_country] => US [patent_app_date] => 2004-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3707 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213040.pdf [firstpage_image] =>[orig_patent_app_number] => 10828894 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/828894
Magnetic random access memory device Apr 19, 2004 Issued
Array ( [id] => 762094 [patent_doc_number] => 07016242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Semiconductor memory apparatus and self-repair method' [patent_app_type] => utility [patent_app_number] => 10/823572 [patent_app_country] => US [patent_app_date] => 2004-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11716 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016242.pdf [firstpage_image] =>[orig_patent_app_number] => 10823572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/823572
Semiconductor memory apparatus and self-repair method Apr 13, 2004 Issued
Array ( [id] => 7244122 [patent_doc_number] => 20040257876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Method for reading a nonvolatile memory device and nonvolatile memory device implementing the reading method' [patent_app_type] => new [patent_app_number] => 10/820458 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7125 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257876.pdf [firstpage_image] =>[orig_patent_app_number] => 10820458 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820458
Method for reading a nonvolatile memory device and nonvolatile memory device implementing the reading method Apr 7, 2004 Issued
Array ( [id] => 1007143 [patent_doc_number] => 06906954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Semiconductor integrated circuit and nonvolatile memory element' [patent_app_type] => utility [patent_app_number] => 10/817820 [patent_app_country] => US [patent_app_date] => 2004-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 22391 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906954.pdf [firstpage_image] =>[orig_patent_app_number] => 10817820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/817820
Semiconductor integrated circuit and nonvolatile memory element Apr 5, 2004 Issued
Array ( [id] => 7243927 [patent_doc_number] => 20040257852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Method of storing data in ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/816854 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6008 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257852.pdf [firstpage_image] =>[orig_patent_app_number] => 10816854 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816854
Method of storing data in ferroelectric memory device Apr 4, 2004 Issued
Array ( [id] => 701778 [patent_doc_number] => 07068546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier' [patent_app_type] => utility [patent_app_number] => 10/815856 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2811 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068546.pdf [firstpage_image] =>[orig_patent_app_number] => 10815856 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815856
Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier Apr 1, 2004 Issued
Array ( [id] => 7451762 [patent_doc_number] => 20040196732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices' [patent_app_type] => new [patent_app_number] => 10/815574 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4153 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196732.pdf [firstpage_image] =>[orig_patent_app_number] => 10815574 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815574
Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices Mar 31, 2004 Issued
Array ( [id] => 572894 [patent_doc_number] => 07158411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Integrated code and data flash memory' [patent_app_type] => utility [patent_app_number] => 10/815370 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5032 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/158/07158411.pdf [firstpage_image] =>[orig_patent_app_number] => 10815370 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815370
Integrated code and data flash memory Mar 31, 2004 Issued
Array ( [id] => 6950938 [patent_doc_number] => 20050226032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'SRAM device having forward body bias control' [patent_app_type] => utility [patent_app_number] => 10/812894 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20050226032.pdf [firstpage_image] =>[orig_patent_app_number] => 10812894 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/812894
SRAM device having forward body bias control Mar 30, 2004 Issued
Menu