Search

Trong Q Phan

Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2827, 2511, 2504, 2824, 2825, 2899, 2818
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10261473 [patent_doc_number] => 20150146469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'MAGNETIC MEMORY DEVICES AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/523663 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10756 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523663 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/523663
MAGNETIC MEMORY DEVICES AND SYSTEMS Oct 23, 2014 Abandoned
Array ( [id] => 10771957 [patent_doc_number] => 20160118113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINES AND DUAL-GATE BIT LINE SELECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/522777 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522777 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/522777
Monolithic three dimensional memory arrays with staggered vertical bit lines and dual-gate bit line select transistors Oct 23, 2014 Issued
Array ( [id] => 10537468 [patent_doc_number] => 09263101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/522345 [patent_app_country] => US [patent_app_date] => 2014-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522345 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/522345
Semiconductor memory device Oct 22, 2014 Issued
Array ( [id] => 10543558 [patent_doc_number] => 09268690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Circuits and methods for providing data to and from arrays of memory cells' [patent_app_type] => utility [patent_app_number] => 14/515849 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3700 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/515849
Circuits and methods for providing data to and from arrays of memory cells Oct 15, 2014 Issued
Array ( [id] => 10576793 [patent_doc_number] => 09299443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Modifying program pulses based on inter-pulse period to reduce program noise' [patent_app_type] => utility [patent_app_number] => 14/500655 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 43 [patent_no_of_words] => 15398 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14500655 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/500655
Modifying program pulses based on inter-pulse period to reduce program noise Sep 28, 2014 Issued
Array ( [id] => 11265695 [patent_doc_number] => 09489995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Memory device for realizing sector erase function and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/494687 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3213 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14494687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/494687
Memory device for realizing sector erase function and operating method thereof Sep 23, 2014 Issued
Array ( [id] => 10321590 [patent_doc_number] => 20150206593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'PROGRAMMING AND VERIFYING FOR NON-VOLATILE STORAGE' [patent_app_type] => utility [patent_app_number] => 14/493039 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17255 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14493039 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/493039
Methods and systems that selectively inhibit and enable programming of non-volatile storage elements Sep 21, 2014 Issued
Array ( [id] => 9795041 [patent_doc_number] => 20150006984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'MANAGING NON-VOLATILE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/486974 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 39375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486974
Managing non-volatile media Sep 14, 2014 Issued
Array ( [id] => 10563290 [patent_doc_number] => 09286971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-15 [patent_title] => 'Method and circuits for low latency initialization of static random access memory' [patent_app_type] => utility [patent_app_number] => 14/482613 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482613 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/482613
Method and circuits for low latency initialization of static random access memory Sep 9, 2014 Issued
Array ( [id] => 10144850 [patent_doc_number] => 09177662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-03 [patent_title] => 'Pre-reading method and programming method for 3D NAND flash memory' [patent_app_type] => utility [patent_app_number] => 14/481953 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1908 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14481953 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/481953
Pre-reading method and programming method for 3D NAND flash memory Sep 9, 2014 Issued
Array ( [id] => 10092840 [patent_doc_number] => 09129668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory' [patent_app_type] => utility [patent_app_number] => 14/476632 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7285 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/476632
Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory Sep 2, 2014 Issued
Array ( [id] => 10966086 [patent_doc_number] => 20140369118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'CONFIGURING STORAGE CELLS' [patent_app_type] => utility [patent_app_number] => 14/475475 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 41703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475475 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475475
Configuring storage cells Sep 1, 2014 Issued
Array ( [id] => 10195568 [patent_doc_number] => 09224481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 14/447051 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4278 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14447051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/447051
Semiconductor storage device Jul 29, 2014 Issued
Array ( [id] => 10931210 [patent_doc_number] => 20140334231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR\nERASING DATA THEREOF' [patent_app_type] => utility [patent_app_number] => 14/338975 [patent_app_country] => US [patent_app_date] => 2014-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11198 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14338975 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/338975
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FORnERASING DATA THEREOF Jul 22, 2014 Abandoned
Array ( [id] => 10151635 [patent_doc_number] => 09183931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors' [patent_app_type] => utility [patent_app_number] => 14/337313 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14337313 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/337313
Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors Jul 21, 2014 Issued
Array ( [id] => 9856402 [patent_doc_number] => 20150036419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'SEMICONDUCTOR APPARATUS AND DATA READING METHOD' [patent_app_type] => utility [patent_app_number] => 14/331025 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6519 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331025 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/331025
SEMICONDUCTOR APPARATUS AND DATA READING METHOD Jul 13, 2014 Abandoned
Array ( [id] => 10904488 [patent_doc_number] => 20140307502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'Far End Resistance Tracking Design with Near End Pre-Charge Control for Faster Recovery Time' [patent_app_type] => utility [patent_app_number] => 14/316857 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316857 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316857
Far end resistance tracking design with near end pre-charge control for faster recovery time Jun 26, 2014 Issued
Array ( [id] => 9833202 [patent_doc_number] => 08942028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Data reprogramming for a data storage device' [patent_app_type] => utility [patent_app_number] => 14/305386 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305386 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/305386
Data reprogramming for a data storage device Jun 15, 2014 Issued
Array ( [id] => 10270054 [patent_doc_number] => 20150155051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING FUSE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/292351 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7398 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292351 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/292351
Semiconductor device having fuse circuit May 29, 2014 Issued
Array ( [id] => 9966295 [patent_doc_number] => 09013919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Data randomization in 3-D memory' [patent_app_type] => utility [patent_app_number] => 14/279017 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 8891 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279017 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/279017
Data randomization in 3-D memory May 14, 2014 Issued
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