Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 647735 [patent_doc_number] => 07120062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Method for soft-programming an electrically erasable nonvolatile memory device, and an electrically erasable nonvolatile memory device implementing the soft-programming method' [patent_app_type] => utility [patent_app_number] => 10/779856 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4793 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120062.pdf [firstpage_image] =>[orig_patent_app_number] => 10779856 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779856
Method for soft-programming an electrically erasable nonvolatile memory device, and an electrically erasable nonvolatile memory device implementing the soft-programming method Feb 16, 2004 Issued
Array ( [id] => 7134718 [patent_doc_number] => 20050180241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Pseudo static random access memory and data refresh method thereof' [patent_app_type] => utility [patent_app_number] => 10/778850 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20050180241.pdf [firstpage_image] =>[orig_patent_app_number] => 10778850 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778850
Pseudo static random access memory and data refresh method thereof Feb 12, 2004 Issued
Array ( [id] => 1038986 [patent_doc_number] => 06873564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Zero latency-zero bus turnaround synchronous flash memory' [patent_app_type] => utility [patent_app_number] => 10/779425 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 14136 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873564.pdf [firstpage_image] =>[orig_patent_app_number] => 10779425 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779425
Zero latency-zero bus turnaround synchronous flash memory Feb 12, 2004 Issued
Array ( [id] => 335302 [patent_doc_number] => 07508716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Sense amplifier for low-supply-voltage nonvolatile memory cells' [patent_app_type] => utility [patent_app_number] => 10/777457 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3663 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508716.pdf [firstpage_image] =>[orig_patent_app_number] => 10777457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777457
Sense amplifier for low-supply-voltage nonvolatile memory cells Feb 11, 2004 Issued
Array ( [id] => 7204412 [patent_doc_number] => 20050052917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Column read amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)' [patent_app_type] => utility [patent_app_number] => 10/776054 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2515 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052917.pdf [firstpage_image] =>[orig_patent_app_number] => 10776054 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776054
Column read amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM) Feb 10, 2004 Issued
Array ( [id] => 7421008 [patent_doc_number] => 20040160801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Active programming and operation of a memory device' [patent_app_type] => new [patent_app_number] => 10/776870 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9548 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160801.pdf [firstpage_image] =>[orig_patent_app_number] => 10776870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776870
Active programming and operation of a memory device Feb 10, 2004 Issued
Array ( [id] => 624912 [patent_doc_number] => 07139192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-21 [patent_title] => 'Programming of multi-level memory cells on a continuous word line' [patent_app_type] => utility [patent_app_number] => 10/773659 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 16002 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139192.pdf [firstpage_image] =>[orig_patent_app_number] => 10773659 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/773659
Programming of multi-level memory cells on a continuous word line Feb 5, 2004 Issued
Array ( [id] => 7225419 [patent_doc_number] => 20040156240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Method of erasing non-volatile semiconductor memory device and such non-volatile semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/772638 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11590 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20040156240.pdf [firstpage_image] =>[orig_patent_app_number] => 10772638 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/772638
Method of erasing non-volatile semiconductor memory device and such non-volatile semiconductor memory device Feb 4, 2004 Issued
Array ( [id] => 7368000 [patent_doc_number] => 20040218439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Process for refreshing a dynamic random access memory' [patent_app_type] => new [patent_app_number] => 10/766291 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6217 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20040218439.pdf [firstpage_image] =>[orig_patent_app_number] => 10766291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766291
Process for refreshing a dynamic random access memory and corresponding device Jan 25, 2004 Issued
Array ( [id] => 1016088 [patent_doc_number] => 06894912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/760402 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7654 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894912.pdf [firstpage_image] =>[orig_patent_app_number] => 10760402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/760402
Semiconductor memory Jan 20, 2004 Issued
Array ( [id] => 7628768 [patent_doc_number] => 06819591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method for erasing a memory sector in virtual ground architecture with reduced leakage current' [patent_app_type] => B1 [patent_app_number] => 10/762071 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819591.pdf [firstpage_image] =>[orig_patent_app_number] => 10762071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/762071
Method for erasing a memory sector in virtual ground architecture with reduced leakage current Jan 19, 2004 Issued
Array ( [id] => 1054771 [patent_doc_number] => 06859407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Memory with auto refresh to designated banks' [patent_app_type] => utility [patent_app_number] => 10/757275 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4113 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859407.pdf [firstpage_image] =>[orig_patent_app_number] => 10757275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757275
Memory with auto refresh to designated banks Jan 13, 2004 Issued
Array ( [id] => 7244239 [patent_doc_number] => 20040257896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA FROM THE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => new [patent_app_number] => 10/753371 [patent_app_country] => US [patent_app_date] => 2004-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257896.pdf [firstpage_image] =>[orig_patent_app_number] => 10753371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753371
Semiconductor memory device and method of reading data from the semiconductor memory device Jan 8, 2004 Issued
Array ( [id] => 1095650 [patent_doc_number] => 06826116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Semiconductor memory device including page latch circuit' [patent_app_type] => B2 [patent_app_number] => 10/751463 [patent_app_country] => US [patent_app_date] => 2004-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 8613 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826116.pdf [firstpage_image] =>[orig_patent_app_number] => 10751463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/751463
Semiconductor memory device including page latch circuit Jan 5, 2004 Issued
Array ( [id] => 1095572 [patent_doc_number] => 06826085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Nonvolatile semiconductor memory device capable of accurately and quickly adjusting step-up voltage' [patent_app_type] => B2 [patent_app_number] => 10/750970 [patent_app_country] => US [patent_app_date] => 2004-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3855 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826085.pdf [firstpage_image] =>[orig_patent_app_number] => 10750970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/750970
Nonvolatile semiconductor memory device capable of accurately and quickly adjusting step-up voltage Jan 4, 2004 Issued
Array ( [id] => 879280 [patent_doc_number] => 07359269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Semiconductor memory device for reducing peak current during refresh operation' [patent_app_type] => utility [patent_app_number] => 10/749350 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3520 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359269.pdf [firstpage_image] =>[orig_patent_app_number] => 10749350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749350
Semiconductor memory device for reducing peak current during refresh operation Dec 30, 2003 Issued
Array ( [id] => 7073713 [patent_doc_number] => 20050146980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Fixed phase clock and strobe signals in daisy chained chips' [patent_app_type] => utility [patent_app_number] => 10/749677 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4463 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146980.pdf [firstpage_image] =>[orig_patent_app_number] => 10749677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749677
Fixed phase clock and strobe signals in daisy chained chips Dec 29, 2003 Issued
Array ( [id] => 7331171 [patent_doc_number] => 20040130959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Semiconductor memory device having a DRAM cell structure and handled as a SRAM' [patent_app_type] => new [patent_app_number] => 10/739374 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10260 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130959.pdf [firstpage_image] =>[orig_patent_app_number] => 10739374 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739374
Semiconductor memory device having a DRAM cell structure and handled as a SRAM Dec 17, 2003 Issued
Array ( [id] => 1118203 [patent_doc_number] => 06801456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Method for programming, erasing and reading a flash memory cell' [patent_app_type] => B1 [patent_app_number] => 10/707474 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6728 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801456.pdf [firstpage_image] =>[orig_patent_app_number] => 10707474 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707474
Method for programming, erasing and reading a flash memory cell Dec 16, 2003 Issued
Array ( [id] => 1110860 [patent_doc_number] => 06809962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Storing data in-non-volatile memory devices' [patent_app_type] => B2 [patent_app_number] => 10/738739 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4913 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809962.pdf [firstpage_image] =>[orig_patent_app_number] => 10738739 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/738739
Storing data in-non-volatile memory devices Dec 15, 2003 Issued
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