Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 784524 [patent_doc_number] => 06992917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Integrated circuit with reduced body effect sensitivity' [patent_app_type] => utility [patent_app_number] => 10/736414 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3802 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992917.pdf [firstpage_image] =>[orig_patent_app_number] => 10736414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/736414
Integrated circuit with reduced body effect sensitivity Dec 14, 2003 Issued
Array ( [id] => 1054742 [patent_doc_number] => 06859391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'EEPROM architecture and programming protocol' [patent_app_type] => utility [patent_app_number] => 10/737676 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2253 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859391.pdf [firstpage_image] =>[orig_patent_app_number] => 10737676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737676
EEPROM architecture and programming protocol Dec 14, 2003 Issued
Array ( [id] => 7451683 [patent_doc_number] => 20040196726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Dense content addressable memory cell' [patent_app_type] => new [patent_app_number] => 10/736350 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2394 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196726.pdf [firstpage_image] =>[orig_patent_app_number] => 10736350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/736350
Dense content addressable memory cell Dec 14, 2003 Issued
Array ( [id] => 517094 [patent_doc_number] => 07200030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/733270 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 8672 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200030.pdf [firstpage_image] =>[orig_patent_app_number] => 10733270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733270
Semiconductor memory device Dec 11, 2003 Issued
Array ( [id] => 383952 [patent_doc_number] => 07307907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'SRAM device and a method of operating the same to reduce leakage current during a sleep mode' [patent_app_type] => utility [patent_app_number] => 10/732970 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5431 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307907.pdf [firstpage_image] =>[orig_patent_app_number] => 10732970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732970
SRAM device and a method of operating the same to reduce leakage current during a sleep mode Dec 10, 2003 Issued
Array ( [id] => 1016140 [patent_doc_number] => 06894934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values' [patent_app_type] => utility [patent_app_number] => 10/728372 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2284 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894934.pdf [firstpage_image] =>[orig_patent_app_number] => 10728372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728372
Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values Dec 3, 2003 Issued
Array ( [id] => 710465 [patent_doc_number] => 07061790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Semiconductor memory device and data write method' [patent_app_type] => utility [patent_app_number] => 10/728176 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8209 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061790.pdf [firstpage_image] =>[orig_patent_app_number] => 10728176 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728176
Semiconductor memory device and data write method Dec 2, 2003 Issued
Array ( [id] => 7287915 [patent_doc_number] => 20040109379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Method of marginal erasure for the testing of flash memories' [patent_app_type] => new [patent_app_number] => 10/725809 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2599 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20040109379.pdf [firstpage_image] =>[orig_patent_app_number] => 10725809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725809
Method of marginal erasure for the testing of flash memories Dec 1, 2003 Issued
Array ( [id] => 7320543 [patent_doc_number] => 20040136250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Semiconductor memory device with improved precharge timing' [patent_app_type] => new [patent_app_number] => 10/725776 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3671 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20040136250.pdf [firstpage_image] =>[orig_patent_app_number] => 10725776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725776
Semiconductor memory device with improved precharge timing Nov 30, 2003 Issued
Array ( [id] => 768606 [patent_doc_number] => 07009893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Range selectable address decoder and frame memory device for processing graphic data at high speed using the same' [patent_app_type] => utility [patent_app_number] => 10/717459 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 9825 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009893.pdf [firstpage_image] =>[orig_patent_app_number] => 10717459 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717459
Range selectable address decoder and frame memory device for processing graphic data at high speed using the same Nov 20, 2003 Issued
Array ( [id] => 7379937 [patent_doc_number] => 20040179385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Ferroelectric memory and method of testing the same' [patent_app_type] => new [patent_app_number] => 10/716565 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 20952 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20040179385.pdf [firstpage_image] =>[orig_patent_app_number] => 10716565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716565
Ferroelectric memory and method of testing the same Nov 19, 2003 Issued
Array ( [id] => 944823 [patent_doc_number] => 06967879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Memory trouble relief circuit' [patent_app_type] => utility [patent_app_number] => 10/716876 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2181 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967879.pdf [firstpage_image] =>[orig_patent_app_number] => 10716876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716876
Memory trouble relief circuit Nov 19, 2003 Issued
Array ( [id] => 7331153 [patent_doc_number] => 20040130952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Circuit and method for transforming data input/output format in parallel bit test' [patent_app_type] => new [patent_app_number] => 10/716773 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2733 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130952.pdf [firstpage_image] =>[orig_patent_app_number] => 10716773 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716773
Circuit and method for transforming data input/output format in parallel bit test Nov 18, 2003 Issued
Array ( [id] => 433654 [patent_doc_number] => 07266031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Internal voltage generator with temperature control' [patent_app_type] => utility [patent_app_number] => 10/716749 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5137 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266031.pdf [firstpage_image] =>[orig_patent_app_number] => 10716749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716749
Internal voltage generator with temperature control Nov 18, 2003 Issued
Array ( [id] => 7102602 [patent_doc_number] => 20050105328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Perpendicular MRAM with high magnetic transition and low programming current' [patent_app_type] => utility [patent_app_number] => 10/715670 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20050105328.pdf [firstpage_image] =>[orig_patent_app_number] => 10715670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715670
Perpendicular MRAM with high magnetic transition and low programming current Nov 16, 2003 Abandoned
Array ( [id] => 713926 [patent_doc_number] => 07057919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-06 [patent_title] => 'Magnetic memory array configuration' [patent_app_type] => utility [patent_app_number] => 10/699155 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 12142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057919.pdf [firstpage_image] =>[orig_patent_app_number] => 10699155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/699155
Magnetic memory array configuration Oct 30, 2003 Issued
Array ( [id] => 906025 [patent_doc_number] => 07336521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Memory pumping circuit' [patent_app_type] => utility [patent_app_number] => 10/696525 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1282 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/336/07336521.pdf [firstpage_image] =>[orig_patent_app_number] => 10696525 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696525
Memory pumping circuit Oct 28, 2003 Issued
Array ( [id] => 6989864 [patent_doc_number] => 20050088901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'CMOS isolation cell for embedded memory in power failure environments' [patent_app_type] => utility [patent_app_number] => 10/695929 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3635 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088901.pdf [firstpage_image] =>[orig_patent_app_number] => 10695929 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695929
CMOS isolation cell for embedded memory in power failure environments Oct 27, 2003 Issued
Array ( [id] => 6989850 [patent_doc_number] => 20050088887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'High efficiency redundancy architecture in SRAM compiler' [patent_app_type] => utility [patent_app_number] => 10/694676 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6008 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088887.pdf [firstpage_image] =>[orig_patent_app_number] => 10694676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/694676
High efficiency redundancy architecture in SRAM compiler Oct 27, 2003 Issued
Array ( [id] => 6989838 [patent_doc_number] => 20050088875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Sensor compensation for environmental variations for magnetic random access memory' [patent_app_type] => utility [patent_app_number] => 10/695572 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2910 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088875.pdf [firstpage_image] =>[orig_patent_app_number] => 10695572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695572
Sensor compensation for environmental variations for magnetic random access memory Oct 27, 2003 Issued
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