Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1038953 [patent_doc_number] => 06873550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Method for programming and erasing an NROM cell' [patent_app_type] => utility [patent_app_number] => 10/636173 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2278 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873550.pdf [firstpage_image] =>[orig_patent_app_number] => 10636173 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636173
Method for programming and erasing an NROM cell Aug 6, 2003 Issued
Array ( [id] => 1149399 [patent_doc_number] => 06778437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Memory circuit for providing word line redundancy in a memory sector' [patent_app_type] => B1 [patent_app_number] => 10/635974 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778437.pdf [firstpage_image] =>[orig_patent_app_number] => 10635974 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635974
Memory circuit for providing word line redundancy in a memory sector Aug 6, 2003 Issued
Array ( [id] => 7374658 [patent_doc_number] => 20040027866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation' [patent_app_type] => new [patent_app_number] => 10/633247 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5756 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027866.pdf [firstpage_image] =>[orig_patent_app_number] => 10633247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633247
Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation Jul 31, 2003 Issued
Array ( [id] => 7392475 [patent_doc_number] => 20040022249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Semiconductor memory device having faulty cells' [patent_app_type] => new [patent_app_number] => 10/629808 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12617 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20040022249.pdf [firstpage_image] =>[orig_patent_app_number] => 10629808 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629808
Semiconductor memory device having faulty cells Jul 29, 2003 Abandoned
Array ( [id] => 7188723 [patent_doc_number] => 20050162888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Write-once polymer memory with e-beam writing and reading' [patent_app_type] => utility [patent_app_number] => 10/627893 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3062 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162888.pdf [firstpage_image] =>[orig_patent_app_number] => 10627893 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627893
Write-once polymer memory with e-beam writing and reading Jul 24, 2003 Abandoned
Array ( [id] => 7297858 [patent_doc_number] => 20040125680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Semiconductor memory device with self-refresh device for reducing power consumption' [patent_app_type] => new [patent_app_number] => 10/625172 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5261 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20040125680.pdf [firstpage_image] =>[orig_patent_app_number] => 10625172 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625172
Semiconductor memory device with self-refresh device for reducing power consumption Jul 21, 2003 Issued
Array ( [id] => 7463624 [patent_doc_number] => 20040120196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF SHORTENING PERIOD REQUIRED FOR PERFORMING DATA RETENTION TEST' [patent_app_type] => new [patent_app_number] => 10/619476 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4107 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20040120196.pdf [firstpage_image] =>[orig_patent_app_number] => 10619476 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619476
Semiconductor integrated circuit device capable of shortening period required for performing data retention test Jul 15, 2003 Issued
Array ( [id] => 959439 [patent_doc_number] => 06954387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Dynamic random access memory with smart refresh scheduler' [patent_app_type] => utility [patent_app_number] => 10/604375 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954387.pdf [firstpage_image] =>[orig_patent_app_number] => 10604375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604375
Dynamic random access memory with smart refresh scheduler Jul 14, 2003 Issued
Array ( [id] => 7150659 [patent_doc_number] => 20050024923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'GAIN CELL MEMORY HAVING READ CYCLE INTERLOCK' [patent_app_type] => utility [patent_app_number] => 10/604374 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024923.pdf [firstpage_image] =>[orig_patent_app_number] => 10604374 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604374
Gain cell memory having read cycle interlock Jul 14, 2003 Issued
Array ( [id] => 6943624 [patent_doc_number] => 20050195673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Magnetic random access memory having memory cells configured by use of tunneling magnetoresistive elements' [patent_app_type] => utility [patent_app_number] => 10/617666 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12808 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195673.pdf [firstpage_image] =>[orig_patent_app_number] => 10617666 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617666
Magnetic random access memory having memory cells configured by use of tunneling magnetoresistive elements Jul 13, 2003 Abandoned
Array ( [id] => 973949 [patent_doc_number] => 06937518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'Programming of a flash memory cell' [patent_app_type] => utility [patent_app_number] => 10/617971 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/937/06937518.pdf [firstpage_image] =>[orig_patent_app_number] => 10617971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617971
Programming of a flash memory cell Jul 9, 2003 Issued
Array ( [id] => 1158314 [patent_doc_number] => 06771538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Semiconductor integrated circuit and nonvolatile memory element' [patent_app_type] => B2 [patent_app_number] => 10/610567 [patent_app_country] => US [patent_app_date] => 2003-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 22305 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771538.pdf [firstpage_image] =>[orig_patent_app_number] => 10610567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/610567
Semiconductor integrated circuit and nonvolatile memory element Jul 1, 2003 Issued
Array ( [id] => 7287845 [patent_doc_number] => 20040109340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Nonvolatile ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/608573 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8334 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20040109340.pdf [firstpage_image] =>[orig_patent_app_number] => 10608573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608573
Nonvolatile ferroelectric memory device Jun 29, 2003 Issued
Array ( [id] => 7352436 [patent_doc_number] => 20040013013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Memory, module with crossed bit lines, and method for reading the memory module' [patent_app_type] => new [patent_app_number] => 10/609874 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4496 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20040013013.pdf [firstpage_image] =>[orig_patent_app_number] => 10609874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609874
Memory, module with crossed bit lines, and method for reading the memory module Jun 29, 2003 Abandoned
Array ( [id] => 1095586 [patent_doc_number] => 06826091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Semiconductor storage apparatus and writing method in semiconductor storage apparatus' [patent_app_type] => B2 [patent_app_number] => 10/460674 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6592 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826091.pdf [firstpage_image] =>[orig_patent_app_number] => 10460674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460674
Semiconductor storage apparatus and writing method in semiconductor storage apparatus Jun 12, 2003 Issued
Array ( [id] => 1108246 [patent_doc_number] => 06813212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Semiconductor memory device and refresh control circuit' [patent_app_type] => B2 [patent_app_number] => 10/450276 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7533 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813212.pdf [firstpage_image] =>[orig_patent_app_number] => 10450276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/450276
Semiconductor memory device and refresh control circuit Jun 10, 2003 Issued
Array ( [id] => 7465226 [patent_doc_number] => 20040095825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'NONVOLATILE MEMORY DEVICE WITH SENSE AMPLIFIER SECURING READING MARGIN' [patent_app_type] => new [patent_app_number] => 10/455479 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13497 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095825.pdf [firstpage_image] =>[orig_patent_app_number] => 10455479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455479
Nonvolatile memory device with sense amplifier securing reading margin Jun 5, 2003 Issued
Array ( [id] => 1038945 [patent_doc_number] => 06873543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 10/448574 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 9239 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873543.pdf [firstpage_image] =>[orig_patent_app_number] => 10448574 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448574
Memory device May 29, 2003 Issued
Array ( [id] => 1104513 [patent_doc_number] => 06816397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'Bi-directional read write data structure and method for memory' [patent_app_type] => B1 [patent_app_number] => 10/448776 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816397.pdf [firstpage_image] =>[orig_patent_app_number] => 10448776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448776
Bi-directional read write data structure and method for memory May 28, 2003 Issued
Array ( [id] => 6807609 [patent_doc_number] => 20030197548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof' [patent_app_type] => new [patent_app_number] => 10/440277 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10800 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197548.pdf [firstpage_image] =>[orig_patent_app_number] => 10440277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440277
Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof May 15, 2003 Issued
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