Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7628770 [patent_doc_number] => 06819589 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Flash memory with pre-detection for data loss' [patent_app_type] => B1 [patent_app_number] => 10/438682 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4585 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819589.pdf [firstpage_image] =>[orig_patent_app_number] => 10438682 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438682
Flash memory with pre-detection for data loss May 14, 2003 Issued
Array ( [id] => 7413858 [patent_doc_number] => 20040228170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'CAPACITIVELY COUPLED SENSING APPARATUS AND METHOD FOR CROSS POINT MAGNETIC RANDOM ACCESS MEMORY DEVICES' [patent_app_type] => new [patent_app_number] => 10/249876 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3789 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20040228170.pdf [firstpage_image] =>[orig_patent_app_number] => 10249876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249876
Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices May 13, 2003 Issued
Array ( [id] => 7386300 [patent_doc_number] => 20040037144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Programming method of the memory cells in a multilevel non-volatile memory device' [patent_app_type] => new [patent_app_number] => 10/438175 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4200 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037144.pdf [firstpage_image] =>[orig_patent_app_number] => 10438175 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438175
Programming method of the memory cells in a multilevel non-volatile memory device May 12, 2003 Issued
Array ( [id] => 1176047 [patent_doc_number] => 06754105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Trench side wall charge trapping dielectric flash memory device' [patent_app_type] => B1 [patent_app_number] => 10/430582 [patent_app_country] => US [patent_app_date] => 2003-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6735 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754105.pdf [firstpage_image] =>[orig_patent_app_number] => 10430582 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/430582
Trench side wall charge trapping dielectric flash memory device May 5, 2003 Issued
Array ( [id] => 1095596 [patent_doc_number] => 06826096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Multiple voltage supply switch' [patent_app_type] => B2 [patent_app_number] => 10/429373 [patent_app_country] => US [patent_app_date] => 2003-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7781 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826096.pdf [firstpage_image] =>[orig_patent_app_number] => 10429373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/429373
Multiple voltage supply switch May 4, 2003 Issued
Array ( [id] => 7368081 [patent_doc_number] => 20040218454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING DRAM REDUNDANCY FUSE LATCHES USING SRAM' [patent_app_type] => new [patent_app_number] => 10/249682 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7417 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20040218454.pdf [firstpage_image] =>[orig_patent_app_number] => 10249682 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249682
Method and apparatus for implementing DRAM redundancy fuse latches using SRAM Apr 29, 2003 Issued
Array ( [id] => 7367922 [patent_doc_number] => 20040218421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Non-volatile memory having a bias on the source electrode for HCI programming' [patent_app_type] => new [patent_app_number] => 10/426282 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3496 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20040218421.pdf [firstpage_image] =>[orig_patent_app_number] => 10426282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426282
Non-volatile memory having a bias on the source electrode for HCI programming Apr 29, 2003 Issued
Array ( [id] => 1199314 [patent_doc_number] => 06728137 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method for programming and reading a plurality of one-time programmable memory blocks' [patent_app_type] => B1 [patent_app_number] => 10/249680 [patent_app_country] => US [patent_app_date] => 2003-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3241 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728137.pdf [firstpage_image] =>[orig_patent_app_number] => 10249680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249680
Method for programming and reading a plurality of one-time programmable memory blocks Apr 28, 2003 Issued
Array ( [id] => 1176012 [patent_doc_number] => 06754101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Refresh techniques for memory data retention' [patent_app_type] => B2 [patent_app_number] => 10/423350 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4874 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754101.pdf [firstpage_image] =>[orig_patent_app_number] => 10423350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/423350
Refresh techniques for memory data retention Apr 24, 2003 Issued
Array ( [id] => 7626093 [patent_doc_number] => 06768673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method of programming and reading a dual cell memory device' [patent_app_type] => B1 [patent_app_number] => 10/422276 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 0 [patent_no_of_words] => 7235 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768673.pdf [firstpage_image] =>[orig_patent_app_number] => 10422276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422276
Method of programming and reading a dual cell memory device Apr 23, 2003 Issued
Array ( [id] => 6724140 [patent_doc_number] => 20030206452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Semiconductor memory device having redundancy system' [patent_app_type] => new [patent_app_number] => 10/421139 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13691 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20030206452.pdf [firstpage_image] =>[orig_patent_app_number] => 10421139 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421139
Semiconductor memory device having redundancy system Apr 22, 2003 Issued
Array ( [id] => 1104537 [patent_doc_number] => 06816408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Memory device with multi-level storage cells' [patent_app_type] => B2 [patent_app_number] => 10/414318 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3476 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816408.pdf [firstpage_image] =>[orig_patent_app_number] => 10414318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414318
Memory device with multi-level storage cells Apr 14, 2003 Issued
Array ( [id] => 6622432 [patent_doc_number] => 20030210590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Apparatus and method of data processing through serial bus' [patent_app_type] => new [patent_app_number] => 10/412581 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2836 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20030210590.pdf [firstpage_image] =>[orig_patent_app_number] => 10412581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/412581
Apparatus and method of data processing through serial bus Apr 13, 2003 Issued
Array ( [id] => 7352482 [patent_doc_number] => 20040013020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Read only memory devices with independently precharged virtual ground and bit lines and methods for operating the same' [patent_app_type] => new [patent_app_number] => 10/406476 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4328 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20040013020.pdf [firstpage_image] =>[orig_patent_app_number] => 10406476 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/406476
Read only memory devices with independently precharged virtual ground and bit lines and methods for operating the same Apr 2, 2003 Issued
Array ( [id] => 1021090 [patent_doc_number] => 06892370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Computerized standard cell library for designing integrated circuits (ICs) with high metal layer intra cell signal wiring, and ICs including same' [patent_app_type] => utility [patent_app_number] => 10/404670 [patent_app_country] => US [patent_app_date] => 2003-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1516 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892370.pdf [firstpage_image] =>[orig_patent_app_number] => 10404670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/404670
Computerized standard cell library for designing integrated circuits (ICs) with high metal layer intra cell signal wiring, and ICs including same Apr 1, 2003 Issued
Array ( [id] => 977277 [patent_doc_number] => 06934177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Ferroelectric memory device and read control method thereof' [patent_app_type] => utility [patent_app_number] => 10/403076 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5778 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934177.pdf [firstpage_image] =>[orig_patent_app_number] => 10403076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/403076
Ferroelectric memory device and read control method thereof Mar 31, 2003 Issued
Array ( [id] => 6677667 [patent_doc_number] => 20030227807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Magnetic logic element and magnetic logic element array' [patent_app_type] => new [patent_app_number] => 10/401676 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227807.pdf [firstpage_image] =>[orig_patent_app_number] => 10401676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/401676
Magnetic logic element and magnetic logic element array Mar 30, 2003 Issued
Array ( [id] => 7392590 [patent_doc_number] => 20040017711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Self reverse bias low-power high-performance storage circuitry and related methods' [patent_app_type] => new [patent_app_number] => 10/402472 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15242 [patent_no_of_claims] => 112 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017711.pdf [firstpage_image] =>[orig_patent_app_number] => 10402472 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/402472
Self reverse bias low-power high-performance storage circuitry and related methods Mar 26, 2003 Issued
Array ( [id] => 7287888 [patent_doc_number] => 20040109363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Ferroelectric storage apparatus, driving method therefor, and driving circuit therefor' [patent_app_type] => new [patent_app_number] => 10/396372 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5737 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20040109363.pdf [firstpage_image] =>[orig_patent_app_number] => 10396372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/396372
Ferroelectric storage apparatus, driving method therefor, and driving circuit therefor Mar 25, 2003 Issued
Array ( [id] => 1042100 [patent_doc_number] => 06870753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Ferroelectric memory' [patent_app_type] => utility [patent_app_number] => 10/396371 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1412 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870753.pdf [firstpage_image] =>[orig_patent_app_number] => 10396371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/396371
Ferroelectric memory Mar 25, 2003 Issued
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