
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7628770
[patent_doc_number] => 06819589
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Flash memory with pre-detection for data loss'
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[patent_app_number] => 10/438682
[patent_app_country] => US
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Array
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[patent_issue_date] => 2004-11-18
[patent_title] => 'CAPACITIVELY COUPLED SENSING APPARATUS AND METHOD FOR CROSS POINT MAGNETIC RANDOM ACCESS MEMORY DEVICES'
[patent_app_type] => new
[patent_app_number] => 10/249876
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249876 | Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices | May 13, 2003 | Issued |
Array
(
[id] => 7386300
[patent_doc_number] => 20040037144
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[patent_issue_date] => 2004-02-26
[patent_title] => 'Programming method of the memory cells in a multilevel non-volatile memory device'
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[patent_app_number] => 10/438175
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/438175 | Programming method of the memory cells in a multilevel non-volatile memory device | May 12, 2003 | Issued |
Array
(
[id] => 1176047
[patent_doc_number] => 06754105
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[patent_issue_date] => 2004-06-22
[patent_title] => 'Trench side wall charge trapping dielectric flash memory device'
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[patent_app_number] => 10/430582
[patent_app_country] => US
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Array
(
[id] => 1095596
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[patent_issue_date] => 2004-11-30
[patent_title] => 'Multiple voltage supply switch'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/429373 | Multiple voltage supply switch | May 4, 2003 | Issued |
Array
(
[id] => 7368081
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[patent_issue_date] => 2004-11-04
[patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING DRAM REDUNDANCY FUSE LATCHES USING SRAM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249682 | Method and apparatus for implementing DRAM redundancy fuse latches using SRAM | Apr 29, 2003 | Issued |
Array
(
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[patent_title] => 'Non-volatile memory having a bias on the source electrode for HCI programming'
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Array
(
[id] => 1199314
[patent_doc_number] => 06728137
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[patent_issue_date] => 2004-04-27
[patent_title] => 'Method for programming and reading a plurality of one-time programmable memory blocks'
[patent_app_type] => B1
[patent_app_number] => 10/249680
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Array
(
[id] => 1176012
[patent_doc_number] => 06754101
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[patent_issue_date] => 2004-06-22
[patent_title] => 'Refresh techniques for memory data retention'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/423350 | Refresh techniques for memory data retention | Apr 24, 2003 | Issued |
Array
(
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[patent_issue_date] => 2004-07-27
[patent_title] => 'Method of programming and reading a dual cell memory device'
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[patent_app_number] => 10/422276
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/422276 | Method of programming and reading a dual cell memory device | Apr 23, 2003 | Issued |
Array
(
[id] => 6724140
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[patent_title] => 'Semiconductor memory device having redundancy system'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/414318 | Memory device with multi-level storage cells | Apr 14, 2003 | Issued |
Array
(
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Array
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Array
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Array
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Array
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Array
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