
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7676207
[patent_doc_number] => 20040153620
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[patent_kind] => A1
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[patent_title] => 'Address scramble'
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Array
(
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[patent_title] => 'Semiconductor memory device and electronic apparatus'
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Array
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[patent_title] => 'Memory device with multi-level storage cells'
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Array
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[patent_issue_date] => 2004-09-07
[patent_title] => 'Charge pump for conductive lines in programmable memory array'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/350482 | DDR memory and storage method | Jan 23, 2003 | Issued |
Array
(
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[patent_title] => 'High voltage drive circuitry aligned with MEMS array'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/348252 | High voltage drive circuitry aligned with MEMS array | Jan 20, 2003 | Issued |
Array
(
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[patent_title] => 'Sense amplifier circuit and method for nonvolatile memory devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/345474 | Sense amplifier circuit and method for nonvolatile memory devices | Jan 14, 2003 | Issued |
Array
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[id] => 6677654
[patent_doc_number] => 20030227794
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[patent_issue_date] => 2003-12-11
[patent_title] => 'SYSTEM AND METHOD FOR ENABLING CHIP LEVEL ERASING AND WRITING FOR MAGNETIC RANDOM ACCESS MEMORY DEVICES'
[patent_app_type] => new
[patent_app_number] => 10/341768
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341768 | System and method for enabling chip level erasing and writing for magnetic random access memory devices | Jan 12, 2003 | Issued |
Array
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[id] => 7392510
[patent_doc_number] => 20040017700
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[patent_title] => 'Method and apparatus for synchronization of row and column access operations'
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Array
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[patent_title] => 'Nonvolatile ferroelectric memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/331584 | Nonvolatile ferroelectric memory device | Dec 30, 2002 | Issued |
Array
(
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Array
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[patent_title] => 'Semiconductor memory device with mode register and method for controlling deep power down mode therein'
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Array
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Array
(
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[patent_title] => 'Reduced read delay for single-ended sensing'
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Array
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[patent_title] => 'NOVEL TWO-TRANSISTOR FLASH CELL FOR LARGE ENDURANCE APPLICATION'
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Array
(
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Array
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Array
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Array
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