Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7676207 [patent_doc_number] => 20040153620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Address scramble' [patent_app_type] => new [patent_app_number] => 10/354188 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2640 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153620.pdf [firstpage_image] =>[orig_patent_app_number] => 10354188 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/354188
Address scramble Jan 29, 2003 Issued
Array ( [id] => 7624501 [patent_doc_number] => 06724675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Semiconductor memory device and electronic apparatus' [patent_app_type] => B2 [patent_app_number] => 10/352985 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 121 [patent_no_of_words] => 18555 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724675.pdf [firstpage_image] =>[orig_patent_app_number] => 10352985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352985
Semiconductor memory device and electronic apparatus Jan 28, 2003 Issued
Array ( [id] => 1275780 [patent_doc_number] => 06654280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Memory device with multi-level storage cells' [patent_app_type] => B2 [patent_app_number] => 10/353434 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3460 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654280.pdf [firstpage_image] =>[orig_patent_app_number] => 10353434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353434
Memory device with multi-level storage cells Jan 27, 2003 Issued
Array ( [id] => 1135665 [patent_doc_number] => 06788578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Charge pump for conductive lines in programmable memory array' [patent_app_type] => B1 [patent_app_number] => 10/351779 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5076 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788578.pdf [firstpage_image] =>[orig_patent_app_number] => 10351779 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/351779
Charge pump for conductive lines in programmable memory array Jan 26, 2003 Issued
Array ( [id] => 6705237 [patent_doc_number] => 20030151971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'DDR memory and storage method' [patent_app_type] => new [patent_app_number] => 10/350482 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2843 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151971.pdf [firstpage_image] =>[orig_patent_app_number] => 10350482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/350482
DDR memory and storage method Jan 23, 2003 Issued
Array ( [id] => 1212302 [patent_doc_number] => 06705165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'High voltage drive circuitry aligned with MEMS array' [patent_app_type] => B2 [patent_app_number] => 10/348252 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 11286 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/705/06705165.pdf [firstpage_image] =>[orig_patent_app_number] => 10348252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/348252
High voltage drive circuitry aligned with MEMS array Jan 20, 2003 Issued
Array ( [id] => 7632123 [patent_doc_number] => 06665213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Sense amplifier circuit and method for nonvolatile memory devices' [patent_app_type] => B1 [patent_app_number] => 10/345474 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4218 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665213.pdf [firstpage_image] =>[orig_patent_app_number] => 10345474 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/345474
Sense amplifier circuit and method for nonvolatile memory devices Jan 14, 2003 Issued
Array ( [id] => 6677654 [patent_doc_number] => 20030227794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'SYSTEM AND METHOD FOR ENABLING CHIP LEVEL ERASING AND WRITING FOR MAGNETIC RANDOM ACCESS MEMORY DEVICES' [patent_app_type] => new [patent_app_number] => 10/341768 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6351 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227794.pdf [firstpage_image] =>[orig_patent_app_number] => 10341768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341768
System and method for enabling chip level erasing and writing for magnetic random access memory devices Jan 12, 2003 Issued
Array ( [id] => 7392510 [patent_doc_number] => 20040017700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Method and apparatus for synchronization of row and column access operations' [patent_app_type] => new [patent_app_number] => 10/337972 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3821 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017700.pdf [firstpage_image] =>[orig_patent_app_number] => 10337972 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337972
Method and apparatus for synchronization of row and column access operations Jan 6, 2003 Issued
Array ( [id] => 7346584 [patent_doc_number] => 20040047173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Nonvolatile ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/331584 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8086 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20040047173.pdf [firstpage_image] =>[orig_patent_app_number] => 10331584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331584
Nonvolatile ferroelectric memory device Dec 30, 2002 Issued
Array ( [id] => 7619100 [patent_doc_number] => 06944089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time' [patent_app_type] => utility [patent_app_number] => 10/334776 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3240 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944089.pdf [firstpage_image] =>[orig_patent_app_number] => 10334776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334776
Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time Dec 30, 2002 Issued
Array ( [id] => 1183285 [patent_doc_number] => 06744687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Semiconductor memory device with mode register and method for controlling deep power down mode therein' [patent_app_type] => B2 [patent_app_number] => 10/331378 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744687.pdf [firstpage_image] =>[orig_patent_app_number] => 10331378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331378
Semiconductor memory device with mode register and method for controlling deep power down mode therein Dec 29, 2002 Issued
Array ( [id] => 1045391 [patent_doc_number] => 06868024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Low voltage sense amplifier for operation under a reduced bit line bias voltage' [patent_app_type] => utility [patent_app_number] => 10/329876 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3799 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868024.pdf [firstpage_image] =>[orig_patent_app_number] => 10329876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329876
Low voltage sense amplifier for operation under a reduced bit line bias voltage Dec 25, 2002 Issued
Array ( [id] => 1032651 [patent_doc_number] => 06879531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Reduced read delay for single-ended sensing' [patent_app_type] => utility [patent_app_number] => 10/324177 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4196 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879531.pdf [firstpage_image] =>[orig_patent_app_number] => 10324177 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/324177
Reduced read delay for single-ended sensing Dec 18, 2002 Issued
Array ( [id] => 7463578 [patent_doc_number] => 20040120188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'NOVEL TWO-TRANSISTOR FLASH CELL FOR LARGE ENDURANCE APPLICATION' [patent_app_type] => new [patent_app_number] => 10/323982 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8453 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20040120188.pdf [firstpage_image] =>[orig_patent_app_number] => 10323982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/323982
Two-transistor flash cell for large endurance application Dec 18, 2002 Issued
Array ( [id] => 1191151 [patent_doc_number] => 06735140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Method and system for performing memory operations of a memory device' [patent_app_type] => B1 [patent_app_number] => 10/326176 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735140.pdf [firstpage_image] =>[orig_patent_app_number] => 10326176 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/326176
Method and system for performing memory operations of a memory device Dec 18, 2002 Issued
Array ( [id] => 7624527 [patent_doc_number] => 06724649 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Memory cell leakage reduction' [patent_app_type] => B1 [patent_app_number] => 10/324178 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3287 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724649.pdf [firstpage_image] =>[orig_patent_app_number] => 10324178 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/324178
Memory cell leakage reduction Dec 18, 2002 Issued
Array ( [id] => 7302459 [patent_doc_number] => 20040114436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Programmable interconnect cell for configuring a field programmable gate array' [patent_app_type] => new [patent_app_number] => 10/319782 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2856 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20040114436.pdf [firstpage_image] =>[orig_patent_app_number] => 10319782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319782
Programmable interconnect cell for configuring a field programmable gate array Dec 11, 2002 Abandoned
Array ( [id] => 1029510 [patent_doc_number] => 06882567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Parallel programming of multiple-bit-per-cell memory cells on a continuous word line' [patent_app_type] => utility [patent_app_number] => 10/313076 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 13727 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882567.pdf [firstpage_image] =>[orig_patent_app_number] => 10313076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313076
Parallel programming of multiple-bit-per-cell memory cells on a continuous word line Dec 5, 2002 Issued
Array ( [id] => 1106845 [patent_doc_number] => 06812753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal' [patent_app_type] => B2 [patent_app_number] => 10/313141 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5388 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812753.pdf [firstpage_image] =>[orig_patent_app_number] => 10313141 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313141
System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal Dec 5, 2002 Issued
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