
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1169443
[patent_doc_number] => 06759882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-06
[patent_title] => 'System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal'
[patent_app_type] => B2
[patent_app_number] => 10/313044
[patent_app_country] => US
[patent_app_date] => 2002-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5356
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/759/06759882.pdf
[firstpage_image] =>[orig_patent_app_number] => 10313044
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313044 | System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal | Dec 5, 2002 | Issued |
Array
(
[id] => 1208637
[patent_doc_number] => 06717850
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-06
[patent_title] => 'Efficient method to detect process induced defects in the gate stack of flash memory devices'
[patent_app_type] => B1
[patent_app_number] => 10/313676
[patent_app_country] => US
[patent_app_date] => 2002-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5857
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/717/06717850.pdf
[firstpage_image] =>[orig_patent_app_number] => 10313676
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313676 | Efficient method to detect process induced defects in the gate stack of flash memory devices | Dec 4, 2002 | Issued |
Array
(
[id] => 1038918
[patent_doc_number] => 06873533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-29
[patent_title] => 'Unbuffered memory system'
[patent_app_type] => utility
[patent_app_number] => 10/309072
[patent_app_country] => US
[patent_app_date] => 2002-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 12196
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/873/06873533.pdf
[firstpage_image] =>[orig_patent_app_number] => 10309072
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/309072 | Unbuffered memory system | Dec 3, 2002 | Issued |
Array
(
[id] => 1016151
[patent_doc_number] => 06894941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-17
[patent_title] => 'RAM having dynamically switchable access modes'
[patent_app_type] => utility
[patent_app_number] => 10/308157
[patent_app_country] => US
[patent_app_date] => 2002-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8794
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/894/06894941.pdf
[firstpage_image] =>[orig_patent_app_number] => 10308157
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/308157 | RAM having dynamically switchable access modes | Dec 2, 2002 | Issued |
Array
(
[id] => 1029504
[patent_doc_number] => 06882563
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-19
[patent_title] => 'Magnetic memory device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/305984
[patent_app_country] => US
[patent_app_date] => 2002-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 31
[patent_no_of_words] => 7145
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/882/06882563.pdf
[firstpage_image] =>[orig_patent_app_number] => 10305984
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305984 | Magnetic memory device and method for manufacturing the same | Nov 28, 2002 | Issued |
Array
(
[id] => 959446
[patent_doc_number] => 06954394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-11
[patent_title] => 'Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions'
[patent_app_type] => utility
[patent_app_number] => 10/307270
[patent_app_country] => US
[patent_app_date] => 2002-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4666
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/954/06954394.pdf
[firstpage_image] =>[orig_patent_app_number] => 10307270
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/307270 | Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions | Nov 26, 2002 | Issued |
Array
(
[id] => 1303663
[patent_doc_number] => 06628545
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Memory circuit for suppressing bit line current leakage'
[patent_app_type] => B1
[patent_app_number] => 10/306080
[patent_app_country] => US
[patent_app_date] => 2002-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3614
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/628/06628545.pdf
[firstpage_image] =>[orig_patent_app_number] => 10306080
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/306080 | Memory circuit for suppressing bit line current leakage | Nov 25, 2002 | Issued |
Array
(
[id] => 6795680
[patent_doc_number] => 20030174553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-18
[patent_title] => 'Semiconductor memory device and method of operation thereof'
[patent_app_type] => new
[patent_app_number] => 10/302953
[patent_app_country] => US
[patent_app_date] => 2002-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 19541
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20030174553.pdf
[firstpage_image] =>[orig_patent_app_number] => 10302953
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/302953 | Semiconductor memory device and method of operation thereof | Nov 24, 2002 | Abandoned |
Array
(
[id] => 1057923
[patent_doc_number] => 06856537
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-15
[patent_title] => 'Thin film magnetic memory device having dummy cell'
[patent_app_type] => utility
[patent_app_number] => 10/299776
[patent_app_country] => US
[patent_app_date] => 2002-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 33
[patent_no_of_words] => 9556
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/856/06856537.pdf
[firstpage_image] =>[orig_patent_app_number] => 10299776
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/299776 | Thin film magnetic memory device having dummy cell | Nov 19, 2002 | Issued |
Array
(
[id] => 7628771
[patent_doc_number] => 06819588
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-16
[patent_title] => 'Memory element, method for structuring a surface, and storage device'
[patent_app_type] => B2
[patent_app_number] => 10/299480
[patent_app_country] => US
[patent_app_date] => 2002-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 6988
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/819/06819588.pdf
[firstpage_image] =>[orig_patent_app_number] => 10299480
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/299480 | Memory element, method for structuring a surface, and storage device | Nov 18, 2002 | Issued |
Array
(
[id] => 1042126
[patent_doc_number] => 06870766
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-22
[patent_title] => 'Multi-level flash memory with temperature compensation'
[patent_app_type] => utility
[patent_app_number] => 10/300485
[patent_app_country] => US
[patent_app_date] => 2002-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 5947
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/870/06870766.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300485
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300485 | Multi-level flash memory with temperature compensation | Nov 18, 2002 | Issued |
Array
(
[id] => 7465095
[patent_doc_number] => 20040095801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-20
[patent_title] => 'Thermally-assisted magnetic writing using an oxide layer and current-induced heating'
[patent_app_type] => new
[patent_app_number] => 10/295678
[patent_app_country] => US
[patent_app_date] => 2002-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4595
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20040095801.pdf
[firstpage_image] =>[orig_patent_app_number] => 10295678
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/295678 | Thermally-assisted magnetic writing using an oxide layer and current-induced heating | Nov 14, 2002 | Issued |
Array
(
[id] => 6622514
[patent_doc_number] => 20030210594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Semiconductor memory device having multi-bit testing function'
[patent_app_type] => new
[patent_app_number] => 10/291776
[patent_app_country] => US
[patent_app_date] => 2002-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12550
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20030210594.pdf
[firstpage_image] =>[orig_patent_app_number] => 10291776
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/291776 | Semiconductor memory device having multi-bit testing function | Nov 11, 2002 | Issued |
Array
(
[id] => 1114794
[patent_doc_number] => 06804142
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-12
[patent_title] => '6F2 3-transistor DRAM gain cell'
[patent_app_type] => B2
[patent_app_number] => 10/292080
[patent_app_country] => US
[patent_app_date] => 2002-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 5205
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/804/06804142.pdf
[firstpage_image] =>[orig_patent_app_number] => 10292080
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/292080 | 6F2 3-transistor DRAM gain cell | Nov 11, 2002 | Issued |
Array
(
[id] => 7358211
[patent_doc_number] => 20040090820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'Low standby power SRAM'
[patent_app_type] => new
[patent_app_number] => 10/290980
[patent_app_country] => US
[patent_app_date] => 2002-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2228
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20040090820.pdf
[firstpage_image] =>[orig_patent_app_number] => 10290980
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/290980 | Low standby power SRAM | Nov 7, 2002 | Abandoned |
Array
(
[id] => 1208633
[patent_doc_number] => 06717848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-06
[patent_title] => 'Sensing circuit in a multi-level flash memory cell'
[patent_app_type] => B2
[patent_app_number] => 10/287779
[patent_app_country] => US
[patent_app_date] => 2002-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4023
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/717/06717848.pdf
[firstpage_image] =>[orig_patent_app_number] => 10287779
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/287779 | Sensing circuit in a multi-level flash memory cell | Nov 4, 2002 | Issued |
Array
(
[id] => 1204581
[patent_doc_number] => 06721194
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-13
[patent_title] => 'Semiconductor memory'
[patent_app_type] => B2
[patent_app_number] => 10/287678
[patent_app_country] => US
[patent_app_date] => 2002-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 7597
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/721/06721194.pdf
[firstpage_image] =>[orig_patent_app_number] => 10287678
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/287678 | Semiconductor memory | Nov 4, 2002 | Issued |
Array
(
[id] => 1208634
[patent_doc_number] => 06717849
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-06
[patent_title] => 'Flash memory device'
[patent_app_type] => B2
[patent_app_number] => 10/287784
[patent_app_country] => US
[patent_app_date] => 2002-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2239
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/717/06717849.pdf
[firstpage_image] =>[orig_patent_app_number] => 10287784
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/287784 | Flash memory device | Nov 4, 2002 | Issued |
Array
(
[id] => 7195330
[patent_doc_number] => 20040085794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Memory cell sensing system and method'
[patent_app_type] => new
[patent_app_number] => 10/286081
[patent_app_country] => US
[patent_app_date] => 2002-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4860
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20040085794.pdf
[firstpage_image] =>[orig_patent_app_number] => 10286081
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/286081 | Memory cell sensing system and method | Oct 31, 2002 | Issued |
Array
(
[id] => 1152008
[patent_doc_number] => 06774704
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'Control circuit for selecting the greater of two voltage signals'
[patent_app_type] => B2
[patent_app_number] => 10/282484
[patent_app_country] => US
[patent_app_date] => 2002-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 5456
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/774/06774704.pdf
[firstpage_image] =>[orig_patent_app_number] => 10282484
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/282484 | Control circuit for selecting the greater of two voltage signals | Oct 27, 2002 | Issued |