Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 754358 [patent_doc_number] => 07023754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Semiconductor device having standby mode and active mode' [patent_app_type] => utility [patent_app_number] => 10/279069 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 10589 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023754.pdf [firstpage_image] =>[orig_patent_app_number] => 10279069 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279069
Semiconductor device having standby mode and active mode Oct 23, 2002 Issued
Array ( [id] => 1194889 [patent_doc_number] => 06731538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Semiconductor memory device including page latch circuit' [patent_app_type] => B2 [patent_app_number] => 10/270673 [patent_app_country] => US [patent_app_date] => 2002-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 8710 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/731/06731538.pdf [firstpage_image] =>[orig_patent_app_number] => 10270673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270673
Semiconductor memory device including page latch circuit Oct 15, 2002 Issued
Array ( [id] => 6808157 [patent_doc_number] => 20030198096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/261776 [patent_app_country] => US [patent_app_date] => 2002-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17839 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20030198096.pdf [firstpage_image] =>[orig_patent_app_number] => 10261776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261776
Semiconductor memory device Oct 1, 2002 Issued
Array ( [id] => 1199264 [patent_doc_number] => 06728125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Bit line selection circuit having hierarchical structure' [patent_app_type] => B2 [patent_app_number] => 10/254478 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3188 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728125.pdf [firstpage_image] =>[orig_patent_app_number] => 10254478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254478
Bit line selection circuit having hierarchical structure Sep 24, 2002 Issued
Array ( [id] => 1342266 [patent_doc_number] => 06597630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Synchronous semiconductor memory device with NOEMI output buffer circuit' [patent_app_type] => B1 [patent_app_number] => 10/253883 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9482 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597630.pdf [firstpage_image] =>[orig_patent_app_number] => 10253883 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253883
Synchronous semiconductor memory device with NOEMI output buffer circuit Sep 24, 2002 Issued
Array ( [id] => 6681993 [patent_doc_number] => 20030117857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Voltage generator for semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/246083 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117857.pdf [firstpage_image] =>[orig_patent_app_number] => 10246083 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246083
Voltage generator for semiconductor memory device Sep 17, 2002 Issued
Array ( [id] => 1319067 [patent_doc_number] => 06614676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Content-addressable memory device' [patent_app_type] => B2 [patent_app_number] => 10/245277 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3478 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614676.pdf [firstpage_image] =>[orig_patent_app_number] => 10245277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245277
Content-addressable memory device Sep 17, 2002 Issued
Array ( [id] => 7632105 [patent_doc_number] => 06665231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Semiconductor device having pipelined dynamic memory' [patent_app_type] => B2 [patent_app_number] => 10/243664 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 12774 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665231.pdf [firstpage_image] =>[orig_patent_app_number] => 10243664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/243664
Semiconductor device having pipelined dynamic memory Sep 15, 2002 Issued
Array ( [id] => 6719673 [patent_doc_number] => 20030053361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'EDRAM based architecture' [patent_app_type] => new [patent_app_number] => 10/242878 [patent_app_country] => US [patent_app_date] => 2002-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1870 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053361.pdf [firstpage_image] =>[orig_patent_app_number] => 10242878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242878
EDRAM based architecture Sep 10, 2002 Abandoned
Array ( [id] => 1158433 [patent_doc_number] => 06771554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Access delay test circuit for self-refreshing DRAM' [patent_app_type] => B1 [patent_app_number] => 10/242284 [patent_app_country] => US [patent_app_date] => 2002-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4631 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771554.pdf [firstpage_image] =>[orig_patent_app_number] => 10242284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242284
Access delay test circuit for self-refreshing DRAM Sep 10, 2002 Issued
Array ( [id] => 718852 [patent_doc_number] => 07054178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Datapath architecture for high area efficiency' [patent_app_type] => utility [patent_app_number] => 10/236384 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2421 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/054/07054178.pdf [firstpage_image] =>[orig_patent_app_number] => 10236384 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/236384
Datapath architecture for high area efficiency Sep 5, 2002 Issued
Array ( [id] => 7440774 [patent_doc_number] => 20040066667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'WRITE CURRENT SHUNTING COMPENSATION' [patent_app_type] => new [patent_app_number] => 10/230280 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1560 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066667.pdf [firstpage_image] =>[orig_patent_app_number] => 10230280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230280
WRITE CURRENT SHUNTING COMPENSATION Aug 28, 2002 Abandoned
Array ( [id] => 7131750 [patent_doc_number] => 20040042242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'SYSTEM AND METHOD TO AVOID VOLTAGE READ ERRORS IN OPEN DIGIT LINE ARRAY DYNAMIC RANDOM ACCESS MEMORIES' [patent_app_type] => new [patent_app_number] => 10/231680 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4909 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20040042242.pdf [firstpage_image] =>[orig_patent_app_number] => 10231680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231680
System and method to avoid voltage read errors in open digit line array dynamic random access memories Aug 28, 2002 Issued
Array ( [id] => 6749132 [patent_doc_number] => 20030043652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Programmed value determining circuit, semiconductor integrated circuit device including the same, and method for determining programmed value' [patent_app_type] => new [patent_app_number] => 10/232785 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10408 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20030043652.pdf [firstpage_image] =>[orig_patent_app_number] => 10232785 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232785
Programmed value determining circuit, semiconductor integrated circuit device including the same, and method for determining programmed value Aug 27, 2002 Issued
Array ( [id] => 1310490 [patent_doc_number] => 06621730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Magnetic random access memory having a vertical write line' [patent_app_type] => B1 [patent_app_number] => 10/228684 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5596 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621730.pdf [firstpage_image] =>[orig_patent_app_number] => 10228684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228684
Magnetic random access memory having a vertical write line Aug 26, 2002 Issued
Array ( [id] => 6837991 [patent_doc_number] => 20030035331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'High density memory cell' [patent_app_type] => new [patent_app_number] => 10/227380 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6244 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20030035331.pdf [firstpage_image] =>[orig_patent_app_number] => 10227380 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227380
High density memory cell Aug 25, 2002 Issued
Array ( [id] => 7386370 [patent_doc_number] => 20040037159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'CONTROLLING A DELAY LOCK LOOP CIRCUIT' [patent_app_type] => new [patent_app_number] => 10/226782 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7317 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037159.pdf [firstpage_image] =>[orig_patent_app_number] => 10226782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226782
Controlling a delay lock loop circuit Aug 22, 2002 Issued
Array ( [id] => 7633738 [patent_doc_number] => 06657882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Semiconductor memory device and various systems mounting them' [patent_app_type] => B2 [patent_app_number] => 10/225239 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 375 [patent_no_of_words] => 67267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657882.pdf [firstpage_image] =>[orig_patent_app_number] => 10225239 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225239
Semiconductor memory device and various systems mounting them Aug 21, 2002 Issued
Array ( [id] => 1216107 [patent_doc_number] => 06711061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Non-volatile semiconductor memory device for selectively re-checking word lines' [patent_app_type] => B2 [patent_app_number] => 10/223488 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4473 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711061.pdf [firstpage_image] =>[orig_patent_app_number] => 10223488 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/223488
Non-volatile semiconductor memory device for selectively re-checking word lines Aug 19, 2002 Issued
Array ( [id] => 7374602 [patent_doc_number] => 20040027855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'DYNAMIC SUB-ARRAY GROUP SELECTION SCHEME' [patent_app_type] => new [patent_app_number] => 10/217182 [patent_app_country] => US [patent_app_date] => 2002-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4844 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027855.pdf [firstpage_image] =>[orig_patent_app_number] => 10217182 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/217182
Dynamic sub-array group selection scheme Aug 11, 2002 Issued
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