
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 409881
[patent_doc_number] => 07286383
[patent_country] => US
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[patent_issue_date] => 2007-10-23
[patent_title] => 'Bit line sharing and word line load reduction for low AC power SRAM architecture'
[patent_app_type] => utility
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[pdf_file] => patents/07/286/07286383.pdf
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Array
(
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[patent_issue_date] => 2005-05-31
[patent_title] => 'Memory device with multi-level storage cells and apparatuses, systems and methods including same'
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Array
(
[id] => 1194942
[patent_doc_number] => 06731558
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[patent_title] => 'Semiconductor device'
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Array
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[patent_issue_date] => 2003-08-07
[patent_title] => 'Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system'
[patent_app_type] => new
[patent_app_number] => 10/209894
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Array
(
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[patent_title] => 'Analog to digital converter utilizing resolution enhancement'
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Array
(
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[patent_doc_number] => 06891752
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[patent_title] => 'System and method for erase voltage control during multiple sector erase of a flash memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/210378 | System and method for erase voltage control during multiple sector erase of a flash memory device | Jul 30, 2002 | Issued |
Array
(
[id] => 6255624
[patent_doc_number] => 20020186040
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[patent_title] => 'Semiconductor logic circuit device of low current consumption'
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Array
(
[id] => 973948
[patent_doc_number] => 06937517
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[patent_issue_date] => 2005-08-30
[patent_title] => 'Clock regulation scheme for varying loads'
[patent_app_type] => utility
[patent_app_number] => 10/197782
[patent_app_country] => US
[patent_app_date] => 2002-07-18
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[firstpage_image] =>[orig_patent_app_number] => 10197782
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197782 | Clock regulation scheme for varying loads | Jul 17, 2002 | Issued |
Array
(
[id] => 1350016
[patent_doc_number] => 06590804
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[patent_issue_date] => 2003-07-08
[patent_title] => 'Adjustable current mode differential amplifier'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/198278 | Adjustable current mode differential amplifier | Jul 15, 2002 | Issued |
Array
(
[id] => 6773214
[patent_doc_number] => 20030016552
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[patent_title] => 'Read only memory'
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Array
(
[id] => 1275733
[patent_doc_number] => 06654270
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[patent_title] => 'Directional coupling memory module'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/191112 | Directional coupling memory module | Jul 9, 2002 | Issued |
Array
(
[id] => 6757614
[patent_doc_number] => 20030005391
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[patent_title] => 'Sensor adjusting circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/191407 | Sensor adjusting circuit | Jul 9, 2002 | Abandoned |
Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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