Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1334754 [patent_doc_number] => 06600690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Sense amplifier for a memory having at least two distinct resistance states' [patent_app_type] => B1 [patent_app_number] => 10/184784 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8600 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600690.pdf [firstpage_image] =>[orig_patent_app_number] => 10184784 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184784
Sense amplifier for a memory having at least two distinct resistance states Jun 27, 2002 Issued
Array ( [id] => 1216184 [patent_doc_number] => 06711087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Limited swing driver circuit' [patent_app_type] => B2 [patent_app_number] => 10/186963 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 16848 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711087.pdf [firstpage_image] =>[orig_patent_app_number] => 10186963 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186963
Limited swing driver circuit Jun 27, 2002 Issued
Array ( [id] => 7425605 [patent_doc_number] => 20040001348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Multiple-mode memory and method for forming same' [patent_app_type] => new [patent_app_number] => 10/184578 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2692 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20040001348.pdf [firstpage_image] =>[orig_patent_app_number] => 10184578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184578
Multiple-mode memory and method for forming same Jun 26, 2002 Issued
Array ( [id] => 6754586 [patent_doc_number] => 20030002362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Method for assessing the quality of a memory unit' [patent_app_type] => new [patent_app_number] => 10/185282 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3113 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20030002362.pdf [firstpage_image] =>[orig_patent_app_number] => 10185282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185282
Method for assessing the quality of a memory unit Jun 26, 2002 Issued
Array ( [id] => 7614419 [patent_doc_number] => 06898111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'SRAM device' [patent_app_type] => utility [patent_app_number] => 10/179980 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3673 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898111.pdf [firstpage_image] =>[orig_patent_app_number] => 10179980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179980
SRAM device Jun 25, 2002 Issued
Array ( [id] => 6824444 [patent_doc_number] => 20030235066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'FERROELECTRIC WRITE ONCE READ ONLY MEMORY FOR ARCHIVAL STORAGE' [patent_app_type] => new [patent_app_number] => 10/177082 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7966 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235066.pdf [firstpage_image] =>[orig_patent_app_number] => 10177082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177082
Ferroelectric write once read only memory for archival storage Jun 20, 2002 Issued
Array ( [id] => 1275781 [patent_doc_number] => 06654281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Nonvolatile nor semiconductor memory device and method for programming the memory device' [patent_app_type] => B2 [patent_app_number] => 10/177884 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4352 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654281.pdf [firstpage_image] =>[orig_patent_app_number] => 10177884 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177884
Nonvolatile nor semiconductor memory device and method for programming the memory device Jun 19, 2002 Issued
Array ( [id] => 1346130 [patent_doc_number] => 06594170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Semiconductor integrated circuit device and semiconductor device system' [patent_app_type] => B2 [patent_app_number] => 10/177583 [patent_app_country] => US [patent_app_date] => 2002-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5349 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594170.pdf [firstpage_image] =>[orig_patent_app_number] => 10177583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177583
Semiconductor integrated circuit device and semiconductor device system Jun 18, 2002 Issued
Array ( [id] => 6638119 [patent_doc_number] => 20030006742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Memory circuit including booster pump for programming voltage generation' [patent_app_type] => new [patent_app_number] => 10/174193 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6668 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20030006742.pdf [firstpage_image] =>[orig_patent_app_number] => 10174193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174193
Memory circuit including booster pump for programming voltage generation Jun 16, 2002 Issued
Array ( [id] => 1598381 [patent_doc_number] => 06492832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing' [patent_app_type] => B2 [patent_app_number] => 10/170911 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3661 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492832.pdf [firstpage_image] =>[orig_patent_app_number] => 10170911 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/170911
Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing Jun 11, 2002 Issued
Array ( [id] => 6257199 [patent_doc_number] => 20020186594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method of re-programming an array of non-volatile memory cells, in particular of the nor architecture flash type, after an erase operation, and a corresponding memory device' [patent_app_type] => new [patent_app_number] => 10/171078 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3788 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20020186594.pdf [firstpage_image] =>[orig_patent_app_number] => 10171078 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/171078
Method of re-programming an array of non-volatile memory cells, in particular of the nor architecture flash type, after an erase operation, and a corresponding memory device Jun 11, 2002 Issued
Array ( [id] => 1427131 [patent_doc_number] => 06522577 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'System and method for enabling chip level erasing and writing for magnetic random access memory devices' [patent_app_type] => B1 [patent_app_number] => 10/163476 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6306 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522577.pdf [firstpage_image] =>[orig_patent_app_number] => 10163476 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163476
System and method for enabling chip level erasing and writing for magnetic random access memory devices Jun 4, 2002 Issued
Array ( [id] => 6808141 [patent_doc_number] => 20030198080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Magnetic random access memory' [patent_app_type] => new [patent_app_number] => 10/160184 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 137 [patent_figures_cnt] => 137 [patent_no_of_words] => 57824 [patent_no_of_claims] => 155 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20030198080.pdf [firstpage_image] =>[orig_patent_app_number] => 10160184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/160184
Magnetic random access memory Jun 3, 2002 Issued
Array ( [id] => 1349958 [patent_doc_number] => 06590799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'On-chip charge distribution measurement circuit' [patent_app_type] => B1 [patent_app_number] => 10/158279 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590799.pdf [firstpage_image] =>[orig_patent_app_number] => 10158279 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/158279
On-chip charge distribution measurement circuit May 28, 2002 Issued
Array ( [id] => 6820747 [patent_doc_number] => 20030218908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor' [patent_app_type] => new [patent_app_number] => 10/154979 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7715 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218908.pdf [firstpage_image] =>[orig_patent_app_number] => 10154979 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154979
Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor May 23, 2002 Issued
Array ( [id] => 1104547 [patent_doc_number] => 06816412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Non-volatile memory cell techniques' [patent_app_type] => B2 [patent_app_number] => 10/151981 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3461 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816412.pdf [firstpage_image] =>[orig_patent_app_number] => 10151981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/151981
Non-volatile memory cell techniques May 20, 2002 Issued
Array ( [id] => 6109156 [patent_doc_number] => 20020172078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/144783 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1927 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20020172078.pdf [firstpage_image] =>[orig_patent_app_number] => 10144783 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144783
Semiconductor memory device May 14, 2002 Issued
Array ( [id] => 6109138 [patent_doc_number] => 20020172071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Integrated semiconductor circuit having transistors that are switched with different frequencies' [patent_app_type] => new [patent_app_number] => 10/146582 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4721 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20020172071.pdf [firstpage_image] =>[orig_patent_app_number] => 10146582 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146582
Integrated semiconductor circuit having transistors that are switched with different frequencies May 14, 2002 Issued
Array ( [id] => 6734439 [patent_doc_number] => 20030012074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'SEMICONDUCTOR MEMORY WITH IMPROVED SOFT ERROR RESISTANCE' [patent_app_type] => new [patent_app_number] => 10/141184 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4605 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20030012074.pdf [firstpage_image] =>[orig_patent_app_number] => 10141184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/141184
Semiconductor memory with improved soft error resistance May 8, 2002 Issued
Array ( [id] => 6423163 [patent_doc_number] => 20020126554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'METHOD FOR PROTECTING AN OVER-ERASURE OF REDUNDANT MEMORY CELLS DURING TEST FOR HIGH-DENSITY NONVOLATILE MEMORY SEMICONDUCTOR DEVICES' [patent_app_type] => new [patent_app_number] => 10/138002 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5138 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126554.pdf [firstpage_image] =>[orig_patent_app_number] => 10138002 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/138002
Method for protecting an over-erasure of redundant memory cells during test for high-density nonvolatile memory semiconductor devices May 2, 2002 Issued
Menu