
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1401774
[patent_doc_number] => 06552924
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Method of reading and logically OR\'ing or AND\'ing a four-transistor memory cell array by rows or columns'
[patent_app_type] => B1
[patent_app_number] => 10/061876
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/061876 | Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns | Jan 30, 2002 | Issued |
Array
(
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[patent_issue_date] => 2003-04-22
[patent_title] => 'Method of reading a four-transistor memory cell array'
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Array
(
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[patent_title] => 'Circuit and method for testing a ferroelectric memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/066182 | Circuit and method for testing a ferroelectric memory device | Jan 30, 2002 | Issued |
Array
(
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[patent_issue_date] => 2003-11-04
[patent_title] => 'Redundant memory circuit for analog semiconductor memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/058786 | Redundant memory circuit for analog semiconductor memory | Jan 29, 2002 | Issued |
Array
(
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[patent_title] => 'SYSTEM FOR PROGRAMMING VERIFICATION'
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Array
(
[id] => 5842237
[patent_doc_number] => 20020131293
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[patent_issue_date] => 2002-09-19
[patent_title] => 'BIT line sense amplifier suppressing a pull-up voltage of a BIT signal and semiconductor memory device having the same'
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[patent_app_number] => 10/060477
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/060477 | BIT line sense amplifier suppressing a pull-up voltage of a BIT signal and semiconductor memory device having the same | Jan 29, 2002 | Abandoned |
| 10/056978 | Method of marginal erasure for the testing of flash memories | Jan 24, 2002 | Abandoned |
Array
(
[id] => 6519964
[patent_doc_number] => 20020136058
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[patent_issue_date] => 2002-09-26
[patent_title] => 'Channel write/erase flash memory cell and its manufacturing method'
[patent_app_type] => new
[patent_app_number] => 09/683580
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Array
(
[id] => 1372289
[patent_doc_number] => 06574139
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[patent_kind] => B2
[patent_issue_date] => 2003-06-03
[patent_title] => 'Method and device for reading dual bit memory cells using multiple reference cells with two side read'
[patent_app_type] => B2
[patent_app_number] => 10/052484
[patent_app_country] => US
[patent_app_date] => 2002-01-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/052484 | Method and device for reading dual bit memory cells using multiple reference cells with two side read | Jan 17, 2002 | Issued |
Array
(
[id] => 1384060
[patent_doc_number] => 06567303
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[patent_issue_date] => 2003-05-20
[patent_title] => 'Charge injection'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/050483 | Charge injection | Jan 15, 2002 | Issued |
Array
(
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[patent_issue_date] => 2003-08-05
[patent_title] => 'Semiconductor memory device having redundancy system'
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[patent_app_number] => 10/045780
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/045780 | Semiconductor memory device having redundancy system | Jan 10, 2002 | Issued |
Array
(
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[patent_title] => 'Controlling output current rambus DRAM'
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Array
(
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Array
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Array
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Array
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Array
(
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Array
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Array
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Array
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