Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1401774 [patent_doc_number] => 06552924 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method of reading and logically OR\'ing or AND\'ing a four-transistor memory cell array by rows or columns' [patent_app_type] => B1 [patent_app_number] => 10/061876 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11102 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552924.pdf [firstpage_image] =>[orig_patent_app_number] => 10061876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061876
Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns Jan 30, 2002 Issued
Array ( [id] => 1401802 [patent_doc_number] => 06552925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method of reading a four-transistor memory cell array' [patent_app_type] => B1 [patent_app_number] => 10/062079 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11089 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552925.pdf [firstpage_image] =>[orig_patent_app_number] => 10062079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062079
Method of reading a four-transistor memory cell array Jan 30, 2002 Issued
Array ( [id] => 6850363 [patent_doc_number] => 20030142565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Circuit and method for testing a ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/066182 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5151 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20030142565.pdf [firstpage_image] =>[orig_patent_app_number] => 10066182 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066182
Circuit and method for testing a ferroelectric memory device Jan 30, 2002 Issued
Array ( [id] => 1288316 [patent_doc_number] => 06643196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Redundant memory circuit for analog semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 10/058786 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 66 [patent_no_of_words] => 30028 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643196.pdf [firstpage_image] =>[orig_patent_app_number] => 10058786 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058786
Redundant memory circuit for analog semiconductor memory Jan 29, 2002 Issued
Array ( [id] => 6850344 [patent_doc_number] => 20030142546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'SYSTEM FOR PROGRAMMING VERIFICATION' [patent_app_type] => new [patent_app_number] => 10/062283 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2248 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20030142546.pdf [firstpage_image] =>[orig_patent_app_number] => 10062283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062283
System for programming verification Jan 29, 2002 Issued
Array ( [id] => 5842237 [patent_doc_number] => 20020131293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'BIT line sense amplifier suppressing a pull-up voltage of a BIT signal and semiconductor memory device having the same' [patent_app_type] => new [patent_app_number] => 10/060477 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3838 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20020131293.pdf [firstpage_image] =>[orig_patent_app_number] => 10060477 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060477
BIT line sense amplifier suppressing a pull-up voltage of a BIT signal and semiconductor memory device having the same Jan 29, 2002 Abandoned
10/056978 Method of marginal erasure for the testing of flash memories Jan 24, 2002 Abandoned
Array ( [id] => 6519964 [patent_doc_number] => 20020136058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Channel write/erase flash memory cell and its manufacturing method' [patent_app_type] => new [patent_app_number] => 09/683580 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136058.pdf [firstpage_image] =>[orig_patent_app_number] => 09683580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683580
Channel write/erase flash memory cell and its manufacturing method Jan 21, 2002 Issued
Array ( [id] => 1372289 [patent_doc_number] => 06574139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Method and device for reading dual bit memory cells using multiple reference cells with two side read' [patent_app_type] => B2 [patent_app_number] => 10/052484 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4260 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574139.pdf [firstpage_image] =>[orig_patent_app_number] => 10052484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052484
Method and device for reading dual bit memory cells using multiple reference cells with two side read Jan 17, 2002 Issued
Array ( [id] => 1384060 [patent_doc_number] => 06567303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Charge injection' [patent_app_type] => B1 [patent_app_number] => 10/050483 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8829 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567303.pdf [firstpage_image] =>[orig_patent_app_number] => 10050483 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050483
Charge injection Jan 15, 2002 Issued
Array ( [id] => 1332170 [patent_doc_number] => 06603689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Semiconductor memory device having redundancy system' [patent_app_type] => B2 [patent_app_number] => 10/045780 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 13495 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603689.pdf [firstpage_image] =>[orig_patent_app_number] => 10045780 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045780
Semiconductor memory device having redundancy system Jan 10, 2002 Issued
Array ( [id] => 1384346 [patent_doc_number] => 06567317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Controlling output current rambus DRAM' [patent_app_type] => B2 [patent_app_number] => 10/032080 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6094 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567317.pdf [firstpage_image] =>[orig_patent_app_number] => 10032080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032080
Controlling output current rambus DRAM Dec 30, 2001 Issued
Array ( [id] => 1413880 [patent_doc_number] => 06542426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Cell data protection circuit in semiconductor memory device and method of driving refresh mode' [patent_app_type] => B2 [patent_app_number] => 10/032079 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5456 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542426.pdf [firstpage_image] =>[orig_patent_app_number] => 10032079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032079
Cell data protection circuit in semiconductor memory device and method of driving refresh mode Dec 30, 2001 Issued
Array ( [id] => 6759913 [patent_doc_number] => 20030123274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'System and method for intermediating communication with a moveable media library utilizing a plurality of partitions' [patent_app_type] => new [patent_app_number] => 10/034580 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7717 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20030123274.pdf [firstpage_image] =>[orig_patent_app_number] => 10034580 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034580
System and method for intermediating communication with a moveable media library utilizing a plurality of partitions Dec 27, 2001 Issued
Array ( [id] => 6762947 [patent_doc_number] => 20030126309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'System and method for managing access to multiple devices in a partitioned data library' [patent_app_type] => new [patent_app_number] => 10/032662 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5539 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126309.pdf [firstpage_image] =>[orig_patent_app_number] => 10032662 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032662
System and method for managing access to multiple devices in a partitioned data library Dec 27, 2001 Issued
Array ( [id] => 1396095 [patent_doc_number] => 06560143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and structure for efficient data verification operation for non-volatile memories' [patent_app_type] => B2 [patent_app_number] => 10/040748 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 9565 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560143.pdf [firstpage_image] =>[orig_patent_app_number] => 10040748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040748
Method and structure for efficient data verification operation for non-volatile memories Dec 27, 2001 Issued
Array ( [id] => 6630137 [patent_doc_number] => 20020086477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Apparatus and a method for a data output circuit in a semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/033682 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3981 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086477.pdf [firstpage_image] =>[orig_patent_app_number] => 10033682 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033682
Apparatus and a method for a data output circuit in a semiconductor memory Dec 26, 2001 Issued
Array ( [id] => 1429361 [patent_doc_number] => 06515907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Complementary non-volatile memory circuit' [patent_app_type] => B2 [patent_app_number] => 10/027076 [patent_app_country] => US [patent_app_date] => 2001-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4687 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515907.pdf [firstpage_image] =>[orig_patent_app_number] => 10027076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/027076
Complementary non-volatile memory circuit Dec 25, 2001 Issued
Array ( [id] => 1418777 [patent_doc_number] => 06535422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Nonvolatile memory system' [patent_app_type] => B2 [patent_app_number] => 10/023882 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8717 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535422.pdf [firstpage_image] =>[orig_patent_app_number] => 10023882 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023882
Nonvolatile memory system Dec 20, 2001 Issued
Array ( [id] => 5964448 [patent_doc_number] => 20020088960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Semiconductor memory device having a word line enable sensing circuit' [patent_app_type] => new [patent_app_number] => 10/020578 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3449 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20020088960.pdf [firstpage_image] =>[orig_patent_app_number] => 10020578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020578
Semiconductor memory device having a word line enable sensing circuit Dec 17, 2001 Issued
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