Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6667710 [patent_doc_number] => 20030112693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Apparatus and method for parallel programming of antifuses' [patent_app_type] => new [patent_app_number] => 10/023280 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4908 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112693.pdf [firstpage_image] =>[orig_patent_app_number] => 10023280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023280
Apparatus and method for parallel programming of antifuses Dec 13, 2001 Issued
Array ( [id] => 6085560 [patent_doc_number] => 20020083289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Circuit and method for controlling buffers in semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/005877 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083289.pdf [firstpage_image] =>[orig_patent_app_number] => 10005877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005877
Circuit and method for controlling buffers in semiconductor memory device Dec 6, 2001 Issued
Array ( [id] => 1425724 [patent_doc_number] => 06525966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method and apparatus for adjusting on-chip current reference for EEPROM sensing' [patent_app_type] => B1 [patent_app_number] => 10/010985 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3234 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525966.pdf [firstpage_image] =>[orig_patent_app_number] => 10010985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010985
Method and apparatus for adjusting on-chip current reference for EEPROM sensing Dec 4, 2001 Issued
Array ( [id] => 6636380 [patent_doc_number] => 20030103370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Ferroelectric memory device and method to sequentially link same' [patent_app_type] => new [patent_app_number] => 10/005676 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4050 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20030103370.pdf [firstpage_image] =>[orig_patent_app_number] => 10005676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005676
Ferroelectric memory input/output apparatus Dec 2, 2001 Issued
Array ( [id] => 6604894 [patent_doc_number] => 20020064078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Semiconductor memory device and voltage level control method thereof' [patent_app_type] => new [patent_app_number] => 10/000178 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4353 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064078.pdf [firstpage_image] =>[orig_patent_app_number] => 10000178 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/000178
Semiconductor memory device and voltage level control method thereof Nov 29, 2001 Issued
Array ( [id] => 6632257 [patent_doc_number] => 20020066002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Integrated magnetoresistive semiconductor memory and fabrication method for the memory' [patent_app_type] => new [patent_app_number] => 09/997983 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1904 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066002.pdf [firstpage_image] =>[orig_patent_app_number] => 09997983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997983
Integrated magnetoresistive semiconductor memory and fabrication method for the memory Nov 28, 2001 Issued
Array ( [id] => 6435539 [patent_doc_number] => 20020176283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/997080 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20020176283.pdf [firstpage_image] =>[orig_patent_app_number] => 09997080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997080
Nonvolatile semiconductor memory device Nov 27, 2001 Issued
Array ( [id] => 6534655 [patent_doc_number] => 20020110042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Synthesizable synchronous static RAM' [patent_app_type] => new [patent_app_number] => 09/988882 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3533 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20020110042.pdf [firstpage_image] =>[orig_patent_app_number] => 09988882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988882
Synthesizable synchronous static RAM Nov 19, 2001 Issued
Array ( [id] => 1431669 [patent_doc_number] => 06504752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Magnetic random access memory' [patent_app_type] => B2 [patent_app_number] => 09/987980 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 22673 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504752.pdf [firstpage_image] =>[orig_patent_app_number] => 09987980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987980
Magnetic random access memory Nov 15, 2001 Issued
Array ( [id] => 6353209 [patent_doc_number] => 20020057592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Distributed storage in semiconductor memory systems' [patent_app_type] => new [patent_app_number] => 10/011184 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5264 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20020057592.pdf [firstpage_image] =>[orig_patent_app_number] => 10011184 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011184
Distributed storage in semiconductor memory systems Nov 12, 2001 Abandoned
Array ( [id] => 5919876 [patent_doc_number] => 20020114210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Semiconductor memory device and information processing unit' [patent_app_type] => new [patent_app_number] => 09/986582 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 19328 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20020114210.pdf [firstpage_image] =>[orig_patent_app_number] => 09986582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986582
Semiconductor memory device and information processing unit Nov 8, 2001 Issued
Array ( [id] => 6287869 [patent_doc_number] => 20020054510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Non-volatile semiconductor memory device for selectively re-checking word lines' [patent_app_type] => new [patent_app_number] => 09/986081 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4460 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20020054510.pdf [firstpage_image] =>[orig_patent_app_number] => 09986081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986081
Non-volatile semiconductor memory device for selectively re-checking word lines Nov 6, 2001 Issued
Array ( [id] => 6353370 [patent_doc_number] => 20020057615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/986082 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18254 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20020057615.pdf [firstpage_image] =>[orig_patent_app_number] => 09986082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986082
Semiconductor memory device Nov 6, 2001 Issued
Array ( [id] => 5937832 [patent_doc_number] => 20020062430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Memory configuration with a central connection area' [patent_app_type] => new [patent_app_number] => 10/014776 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2928 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20020062430.pdf [firstpage_image] =>[orig_patent_app_number] => 10014776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/014776
Memory configuration with a central connection area Nov 6, 2001 Issued
Array ( [id] => 6287842 [patent_doc_number] => 20020054503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Semiconductor memory device having memory cell array structure with improved bit line precharge time and method thereof' [patent_app_type] => new [patent_app_number] => 09/986181 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4322 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20020054503.pdf [firstpage_image] =>[orig_patent_app_number] => 09986181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986181
Semiconductor memory device having memory cell array structure with improved bit line precharge time and method thereof Nov 6, 2001 Issued
Array ( [id] => 1184611 [patent_doc_number] => 06741513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Data memory with a plurality of memory banks' [patent_app_type] => B2 [patent_app_number] => 10/001176 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6824 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741513.pdf [firstpage_image] =>[orig_patent_app_number] => 10001176 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001176
Data memory with a plurality of memory banks Nov 1, 2001 Issued
Array ( [id] => 6868756 [patent_doc_number] => 20030081445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Feedback write method for programmable memory' [patent_app_type] => new [patent_app_number] => 10/001680 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5688 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20030081445.pdf [firstpage_image] =>[orig_patent_app_number] => 10001680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001680
Feedback write method for programmable memory Oct 30, 2001 Issued
Array ( [id] => 6868758 [patent_doc_number] => 20030081447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage' [patent_app_type] => new [patent_app_number] => 09/999379 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20030081447.pdf [firstpage_image] =>[orig_patent_app_number] => 09999379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999379
Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage Oct 30, 2001 Issued
Array ( [id] => 5903507 [patent_doc_number] => 20020141227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Semiconductor device in which storage electrode of capacitor is connected to gate electrode of fet and inspection method thereof' [patent_app_type] => new [patent_app_number] => 09/984779 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20020141227.pdf [firstpage_image] =>[orig_patent_app_number] => 09984779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984779
Semiconductor device in which storage electrode of capacitor is connected to gate electrode of FET and inspection method thereof Oct 30, 2001 Issued
Array ( [id] => 1469980 [patent_doc_number] => 06459613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Current-mode identifying circuit for multilevel flash memories' [patent_app_type] => B1 [patent_app_number] => 09/984285 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3047 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459613.pdf [firstpage_image] =>[orig_patent_app_number] => 09984285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984285
Current-mode identifying circuit for multilevel flash memories Oct 28, 2001 Issued
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