Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1383934 [patent_doc_number] => 06567296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Memory device' [patent_app_type] => B1 [patent_app_number] => 10/041684 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567296.pdf [firstpage_image] =>[orig_patent_app_number] => 10041684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/041684
Memory device Oct 23, 2001 Issued
Array ( [id] => 6094344 [patent_doc_number] => 20020051392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/983076 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4474 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20020051392.pdf [firstpage_image] =>[orig_patent_app_number] => 09983076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983076
Semiconductor memory device Oct 22, 2001 Issued
Array ( [id] => 1482977 [patent_doc_number] => 06452862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Semiconductor memory device having hierarchical word line structure' [patent_app_type] => B1 [patent_app_number] => 09/981981 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13544 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452862.pdf [firstpage_image] =>[orig_patent_app_number] => 09981981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981981
Semiconductor memory device having hierarchical word line structure Oct 18, 2001 Issued
Array ( [id] => 6423293 [patent_doc_number] => 20020126565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Semiconductor integrated circuit device with internal clock generating circuit' [patent_app_type] => new [patent_app_number] => 09/977275 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11776 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126565.pdf [firstpage_image] =>[orig_patent_app_number] => 09977275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977275
Semiconductor integrated circuit device with internal clock generating circuit Oct 15, 2001 Issued
Array ( [id] => 7644642 [patent_doc_number] => 06473331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Semiconductor memory device and various systems mounting them' [patent_app_type] => B2 [patent_app_number] => 09/976154 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 371 [patent_no_of_words] => 67357 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473331.pdf [firstpage_image] =>[orig_patent_app_number] => 09976154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976154
Semiconductor memory device and various systems mounting them Oct 14, 2001 Issued
Array ( [id] => 6094301 [patent_doc_number] => 20020051379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Loadless 4T SRAM cell with PMOS drivers' [patent_app_type] => new [patent_app_number] => 09/976983 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2556 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20020051379.pdf [firstpage_image] =>[orig_patent_app_number] => 09976983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976983
Loadless 4T SRAM cell with PMOS drivers Oct 11, 2001 Issued
Array ( [id] => 1457808 [patent_doc_number] => 06462995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/975149 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462995.pdf [firstpage_image] =>[orig_patent_app_number] => 09975149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975149
Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device Oct 11, 2001 Issued
Array ( [id] => 1346330 [patent_doc_number] => 06594184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'System and method for accessing a memory array which tolerates non-exclusive read select enables' [patent_app_type] => B2 [patent_app_number] => 09/948180 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3699 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594184.pdf [firstpage_image] =>[orig_patent_app_number] => 09948180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948180
System and method for accessing a memory array which tolerates non-exclusive read select enables Sep 5, 2001 Issued
Array ( [id] => 5998454 [patent_doc_number] => 20020027810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/946480 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8410 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027810.pdf [firstpage_image] =>[orig_patent_app_number] => 09946480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946480
Semiconductor integrated circuit Sep 5, 2001 Issued
Array ( [id] => 1416831 [patent_doc_number] => 06528839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Semiconductor integrated circuit and nonvolatile memory element' [patent_app_type] => B2 [patent_app_number] => 09/942902 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 22384 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528839.pdf [firstpage_image] =>[orig_patent_app_number] => 09942902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942902
Semiconductor integrated circuit and nonvolatile memory element Aug 30, 2001 Issued
Array ( [id] => 5950046 [patent_doc_number] => 20020006054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Semiconductor integrated circuit and nonvolatile memory element' [patent_app_type] => new [patent_app_number] => 09/942825 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22531 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006054.pdf [firstpage_image] =>[orig_patent_app_number] => 09942825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942825
Semiconductor integrated circuit and nonvolatile memory element Aug 30, 2001 Issued
Array ( [id] => 1599629 [patent_doc_number] => 06385079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Methods and structure for maximizing signal to noise ratio in resistive array' [patent_app_type] => B1 [patent_app_number] => 09/944680 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385079.pdf [firstpage_image] =>[orig_patent_app_number] => 09944680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944680
Methods and structure for maximizing signal to noise ratio in resistive array Aug 30, 2001 Issued
Array ( [id] => 1314889 [patent_doc_number] => 06618283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal' [patent_app_type] => B2 [patent_app_number] => 09/944484 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5311 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618283.pdf [firstpage_image] =>[orig_patent_app_number] => 09944484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944484
System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal Aug 28, 2001 Issued
Array ( [id] => 1249648 [patent_doc_number] => 06674672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/942284 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2849 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674672.pdf [firstpage_image] =>[orig_patent_app_number] => 09942284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942284
Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits Aug 26, 2001 Issued
Array ( [id] => 1499191 [patent_doc_number] => 06404671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Data-dependent field compensation for writing magnetic random access memories' [patent_app_type] => B1 [patent_app_number] => 09/933584 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404671.pdf [firstpage_image] =>[orig_patent_app_number] => 09933584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933584
Data-dependent field compensation for writing magnetic random access memories Aug 20, 2001 Issued
Array ( [id] => 1430745 [patent_doc_number] => 06526547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method for efficient manufacturing of integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/932064 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8004 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526547.pdf [firstpage_image] =>[orig_patent_app_number] => 09932064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932064
Method for efficient manufacturing of integrated circuits Aug 16, 2001 Issued
Array ( [id] => 1457777 [patent_doc_number] => 06462987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'Direct-comparison reading circuit for a nonvolatile memory array' [patent_app_type] => B2 [patent_app_number] => 09/930875 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4488 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462987.pdf [firstpage_image] =>[orig_patent_app_number] => 09930875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930875
Direct-comparison reading circuit for a nonvolatile memory array Aug 14, 2001 Issued
Array ( [id] => 1461184 [patent_doc_number] => 06426909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/924779 [patent_app_country] => US [patent_app_date] => 2001-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 23720 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426909.pdf [firstpage_image] =>[orig_patent_app_number] => 09924779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924779
Semiconductor memory Aug 8, 2001 Issued
Array ( [id] => 1517658 [patent_doc_number] => 06421276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method and apparatus for controlling erase operations of a non-volatile memory system' [patent_app_type] => B1 [patent_app_number] => 09/927277 [patent_app_country] => US [patent_app_date] => 2001-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7221 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421276.pdf [firstpage_image] =>[orig_patent_app_number] => 09927277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927277
Method and apparatus for controlling erase operations of a non-volatile memory system Aug 8, 2001 Issued
Array ( [id] => 1194905 [patent_doc_number] => 06731545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method and apparatus for reducing worst case power' [patent_app_type] => B2 [patent_app_number] => 09/924856 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 7818 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/731/06731545.pdf [firstpage_image] =>[orig_patent_app_number] => 09924856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924856
Method and apparatus for reducing worst case power Aug 6, 2001 Issued
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