Trong Q. Phan

Array ( [id] => 1403431 [patent_doc_number] => 06545528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/923576 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 13075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545528.pdf [firstpage_image] =>[orig_patent_app_number] => 09923576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507403 [patent_doc_number] => 06466495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-15 [patent_title] => 'Electronic circuit, test-apparatus assembly, and method for outputting a data item' [patent_app_type] => B2 [patent_app_number] => 09/922476 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2496 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466495.pdf [firstpage_image] =>[orig_patent_app_number] => 09922476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6714780 [patent_doc_number] => 20030026128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'SENSE AMPLIFIER CIRCUIT AND METHOD FOR NONVOLATILE MEMORY DEVICES' [patent_app_type] => new [patent_app_number] => 09/922177 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4210 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20030026128.pdf [firstpage_image] =>[orig_patent_app_number] => 09922177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1603877 [patent_doc_number] => 06434060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Write pulse limiting for worm storage device' [patent_app_type] => B1 [patent_app_number] => 09/917882 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3368 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434060.pdf [firstpage_image] =>[orig_patent_app_number] => 09917882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6488593 [patent_doc_number] => 20020024830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Content addressable memory using part of memory region to store data which should not be erased' [patent_app_type] => new [patent_app_number] => 09/916676 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024830.pdf [firstpage_image] =>[orig_patent_app_number] => 09916676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1469989 [patent_doc_number] => 06459615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Non-volatile memory cell array with shared erase device' [patent_app_type] => B1 [patent_app_number] => 09/910980 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4171 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459615.pdf [firstpage_image] =>[orig_patent_app_number] => 09910980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5919853 [patent_doc_number] => 20020114203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT WITH VARIABLE BIT LINE PRECHARGING VOLTAGE' [patent_app_type] => new [patent_app_number] => 09/909976 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6590 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20020114203.pdf [firstpage_image] =>[orig_patent_app_number] => 09909976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585314 [patent_doc_number] => 06424563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-23 [patent_title] => 'MRAM memory cell' [patent_app_type] => B2 [patent_app_number] => 09/907778 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2279 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424563.pdf [firstpage_image] =>[orig_patent_app_number] => 09907778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5887284 [patent_doc_number] => 20020012281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Configuration for implementing redundancy for a memory chip' [patent_app_type] => new [patent_app_number] => 09/907783 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2158 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20020012281.pdf [firstpage_image] =>[orig_patent_app_number] => 09907783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7012905 [patent_doc_number] => 20010050624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Reduction of aperture distortion in parallel A/D converters' [patent_app_type] => new [patent_app_number] => 09/907268 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1849 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20010050624.pdf [firstpage_image] =>[orig_patent_app_number] => 09907268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6885475 [patent_doc_number] => 20010039640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Method and apparatus for wiring integrated circuits with multiple power buses based on performance' [patent_app_type] => new [patent_app_number] => 09/905924 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3004 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039640.pdf [firstpage_image] =>[orig_patent_app_number] => 09905924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7064216 [patent_doc_number] => 20010043502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Semiconductor memory device capable of efficient memory cell select operation with reduced element count' [patent_app_type] => new [patent_app_number] => 09/906147 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 14995 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043502.pdf [firstpage_image] =>[orig_patent_app_number] => 09906147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1523374 [patent_doc_number] => 06414896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor memory device having column redundancy scheme to improve redundancy efficiency' [patent_app_type] => B1 [patent_app_number] => 09/905376 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6663 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414896.pdf [firstpage_image] =>[orig_patent_app_number] => 09905376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6534293 [patent_doc_number] => 20020110017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Voltage generator for semiconductor device' [patent_app_type] => new [patent_app_number] => 09/903731 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7848 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20020110017.pdf [firstpage_image] =>[orig_patent_app_number] => 09903731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1398658 [patent_doc_number] => 06556505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Clock phase adjustment method, and integrated circuit and design method therefor' [patent_app_type] => B1 [patent_app_number] => 09/868178 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 20037 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556505.pdf [firstpage_image] =>[orig_patent_app_number] => 09868178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1457866 [patent_doc_number] => 06463006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/902605 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6271 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463006.pdf [firstpage_image] =>[orig_patent_app_number] => 09902605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1463707 [patent_doc_number] => 06392921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Driving circuit for non destructive non volatile ferroelectric random access memory' [patent_app_type] => B1 [patent_app_number] => 09/900184 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2248 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392921.pdf [firstpage_image] =>[orig_patent_app_number] => 09900184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1340181 [patent_doc_number] => 06601225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Semiconductor device having definite size of input/output blocks and its designing method' [patent_app_type] => B2 [patent_app_number] => 09/899351 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 2511 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601225.pdf [firstpage_image] =>[orig_patent_app_number] => 09899351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1210588 [patent_doc_number] => 06718523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Reduced pessimism clock gating tests for a timing analysis tool' [patent_app_type] => B2 [patent_app_number] => 09/899413 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8269 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718523.pdf [firstpage_image] =>[orig_patent_app_number] => 09899413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1372174 [patent_doc_number] => 06574132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits' [patent_app_type] => B2 [patent_app_number] => 09/897280 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1130 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574132.pdf [firstpage_image] =>[orig_patent_app_number] => 09897280 [rel_patent_id] =>[rel_patent_doc_number] =>)