
Trong Q. Phan
Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2511, 2825, 2899, 2818, 2827, 2824, 2504 |
| Total Applications | 3077 |
| Issued Applications | 2717 |
| Pending Applications | 50 |
| Abandoned Applications | 311 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5998485
[patent_doc_number] => 20020027826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Column decoding apparatus for use in a semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 09/895882
[patent_app_country] => US
[patent_app_date] => 2001-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0027/20020027826.pdf
[firstpage_image] =>[orig_patent_app_number] => 09895882
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/895882 | Column decoding apparatus for use in a semiconductor memory device | Jun 28, 2001 | Issued |
Array
(
[id] => 6139705
[patent_doc_number] => 20020001233
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[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Read protection circuit of nonvolatile memory'
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[patent_app_number] => 09/892984
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/892984 | Read protection circuit of nonvolatile memory | Jun 26, 2001 | Issued |
Array
(
[id] => 6320992
[patent_doc_number] => 20020196652
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[patent_issue_date] => 2002-12-26
[patent_title] => 'Read only memory structure'
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[patent_app_number] => 09/888878
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[patent_app_date] => 2001-06-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888878 | Read only memory structure | Jun 24, 2001 | Issued |
Array
(
[id] => 6986282
[patent_doc_number] => 20010036114
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[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Semiconductor memory device having faulty cells'
[patent_app_type] => new
[patent_app_number] => 09/886133
[patent_app_country] => US
[patent_app_date] => 2001-06-22
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[pdf_file] => publications/A1/0036/20010036114.pdf
[firstpage_image] =>[orig_patent_app_number] => 09886133
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/886133 | Semiconductor memory device having faulty cells | Jun 21, 2001 | Issued |
Array
(
[id] => 6986290
[patent_doc_number] => 20010036122
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[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/885066
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[firstpage_image] =>[orig_patent_app_number] => 09885066
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885066 | Semiconductor device | Jun 20, 2001 | Issued |
Array
(
[id] => 1599673
[patent_doc_number] => 06385090
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[patent_issue_date] => 2002-05-07
[patent_title] => 'Semiconductor nonvolatile memory using floating gate'
[patent_app_type] => B1
[patent_app_number] => 09/883377
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[firstpage_image] =>[orig_patent_app_number] => 09883377
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/883377 | Semiconductor nonvolatile memory using floating gate | Jun 18, 2001 | Issued |
Array
(
[id] => 6014055
[patent_doc_number] => 20020101769
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[patent_issue_date] => 2002-08-01
[patent_title] => 'High frequency pulse width modulation driver, particularly useful for electrostatically actuated MEMS array'
[patent_app_type] => new
[patent_app_number] => 09/884676
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[pdf_file] => publications/A1/0101/20020101769.pdf
[firstpage_image] =>[orig_patent_app_number] => 09884676
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/884676 | High frequency pulse width modulation driver, particularly useful for electrostatically actuated MEMS array | Jun 18, 2001 | Issued |
Array
(
[id] => 5903618
[patent_doc_number] => 20020141268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => '1-T MEMORY STRUCTURE CAPABLE OF PERFORMING HIDDEN REFRESH AND AN OPERATING METHOD APPLIED THERETO'
[patent_app_type] => new
[patent_app_number] => 09/880784
[patent_app_country] => US
[patent_app_date] => 2001-06-15
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[pdf_file] => publications/A1/0141/20020141268.pdf
[firstpage_image] =>[orig_patent_app_number] => 09880784
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/880784 | 1-T memory structure capable of performing hidden refresh and an operating method applied thereto | Jun 14, 2001 | Issued |
Array
(
[id] => 7645834
[patent_doc_number] => 06477689
[patent_country] => US
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[patent_issue_date] => 2002-11-05
[patent_title] => 'Architectural structure of a process netlist design tool'
[patent_app_type] => B1
[patent_app_number] => 09/880444
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/880444 | Architectural structure of a process netlist design tool | Jun 12, 2001 | Issued |
Array
(
[id] => 6999304
[patent_doc_number] => 20010053087
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[patent_issue_date] => 2001-12-20
[patent_title] => 'Method for driving semiconductor memory'
[patent_app_type] => new
[patent_app_number] => 09/879079
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/879079 | Method for driving semiconductor memory | Jun 12, 2001 | Issued |
Array
(
[id] => 1366039
[patent_doc_number] => 06581193
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[patent_title] => 'Apparatus and methods for modeling process effects and imaging effects in scanning electron microscopy'
[patent_app_type] => B1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/881451 | Apparatus and methods for modeling process effects and imaging effects in scanning electron microscopy | Jun 12, 2001 | Issued |
Array
(
[id] => 1513525
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[patent_title] => 'RTL back annotator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/879297 | RTL back annotator | Jun 11, 2001 | Issued |
Array
(
[id] => 1509167
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[patent_title] => '-discrepant self-test technique'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/879845 | -discrepant self-test technique | Jun 11, 2001 | Issued |
Array
(
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Array
(
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Array
(
[id] => 1564255
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/879076 | Arrangement of bitline boosting capacitor in semiconductor memory device | Jun 10, 2001 | Issued |
| 09/874212 | Semiconductor memory device and method of operation thereof | Jun 5, 2001 | Abandoned |
Array
(
[id] => 1513521
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[patent_title] => 'Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock trees'
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Array
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Array
(
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