Trong Q. Phan

Array ( [id] => 1567722 [patent_doc_number] => 06438730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'RTL code optimization for resource sharing structures' [patent_app_type] => B1 [patent_app_number] => 09/866661 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2444 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438730.pdf [firstpage_image] =>[orig_patent_app_number] => 09866661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6226718 [patent_doc_number] => 20020004875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Memory device' [patent_app_type] => new [patent_app_number] => 09/866780 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1976 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004875.pdf [firstpage_image] =>[orig_patent_app_number] => 09866780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6223022 [patent_doc_number] => 20020003724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Boosted voltage generating circuit and semiconductor memory device having the same' [patent_app_type] => new [patent_app_number] => 09/864181 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12422 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003724.pdf [firstpage_image] =>[orig_patent_app_number] => 09864181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1337782 [patent_doc_number] => 06604234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Method of designing/manufacturing semiconductor integrated circuit device using combined exposure pattern and semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/864312 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6958 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604234.pdf [firstpage_image] =>[orig_patent_app_number] => 09864312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7639162 [patent_doc_number] => 06396755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory' [patent_app_type] => B2 [patent_app_number] => 09/864978 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4689 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396755.pdf [firstpage_image] =>[orig_patent_app_number] => 09864978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6901167 [patent_doc_number] => 20010022750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/860911 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022750.pdf [firstpage_image] =>[orig_patent_app_number] => 09860911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6109155 [patent_doc_number] => 20020172077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'COLUMN DECODER WITH INCREASED IMMUNITY TO HIGH VOLTAGE BREAKDOWN' [patent_app_type] => new [patent_app_number] => 09/862277 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2326 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20020172077.pdf [firstpage_image] =>[orig_patent_app_number] => 09862277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6062006 [patent_doc_number] => 20020031039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Semiconductor memory' [patent_app_type] => new [patent_app_number] => 09/858761 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031039.pdf [firstpage_image] =>[orig_patent_app_number] => 09858761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1463785 [patent_doc_number] => 06392952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Memory refresh circuit and memory refresh method' [patent_app_type] => B1 [patent_app_number] => 09/855977 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2767 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392952.pdf [firstpage_image] =>[orig_patent_app_number] => 09855977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6882136 [patent_doc_number] => 20010048608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Magnetic random access memory circuit' [patent_app_type] => new [patent_app_number] => 09/854481 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11446 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048608.pdf [firstpage_image] =>[orig_patent_app_number] => 09854481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1470085 [patent_doc_number] => 06459649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-01 [patent_title] => 'Address generator for generating addresses for an on-chip trim circuit' [patent_app_type] => B2 [patent_app_number] => 09/854258 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1952 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459649.pdf [firstpage_image] =>[orig_patent_app_number] => 09854258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6546598 [patent_doc_number] => 20020163823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'METHOD AND APPARATUS FOR CONTENT ADDRESSABLE MEMORY WITH A PARTITIONED MATCH LINE' [patent_app_type] => new [patent_app_number] => 09/850882 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4026 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20020163823.pdf [firstpage_image] =>[orig_patent_app_number] => 09850882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6833649 [patent_doc_number] => 20030161194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Matchline sense circuit and method' [patent_app_type] => new [patent_app_number] => 10/258580 [patent_app_country] => US [patent_app_date] => 2003-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8943 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161194.pdf [firstpage_image] =>[orig_patent_app_number] => 10258580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6891650 [patent_doc_number] => 20010017812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Negative voltage generating circuit with high control responsiveness which can be formed using transistor with low breakdown voltage and semiconductor memory device including the same' [patent_app_type] => new [patent_app_number] => 09/843691 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6571 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017812.pdf [firstpage_image] =>[orig_patent_app_number] => 09843691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644635 [patent_doc_number] => 06473338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Analog voltage supply circuit for a non-volatile memory' [patent_app_type] => B2 [patent_app_number] => 09/840884 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20444 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473338.pdf [firstpage_image] =>[orig_patent_app_number] => 09840884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5950051 [patent_doc_number] => 20020006059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Method for minimizing program disturb in a memory cell' [patent_app_type] => new [patent_app_number] => 09/839236 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7604 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006059.pdf [firstpage_image] =>[orig_patent_app_number] => 09839236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7095211 [patent_doc_number] => 20010034877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Photomask pattern shape correction method and corrected photomask' [patent_app_type] => new [patent_app_number] => 09/837957 [patent_app_country] => US [patent_app_date] => 2001-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3619 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034877.pdf [firstpage_image] =>[orig_patent_app_number] => 09837957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1485228 [patent_doc_number] => 06453443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method for cell modeling and timing verification of chip designs with voltage drop' [patent_app_type] => B1 [patent_app_number] => 09/835028 [patent_app_country] => US [patent_app_date] => 2001-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1714 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453443.pdf [firstpage_image] =>[orig_patent_app_number] => 09835028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5886334 [patent_doc_number] => 20020011868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Very fine grain field programmable gate array architecture and circuitry' [patent_app_type] => new [patent_app_number] => 09/829096 [patent_app_country] => US [patent_app_date] => 2001-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5612 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20020011868.pdf [firstpage_image] =>[orig_patent_app_number] => 09829096 [rel_patent_id] =>[rel_patent_doc_number] =>)