Search

Trong Q. Phan

Examiner (ID: 14718, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2511, 2825, 2899, 2818, 2827, 2824, 2504
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1463715 [patent_doc_number] => 06392924 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Array for forming magnetoresistive random access memory with pseudo spin valve' [patent_app_type] => B1 [patent_app_number] => 09/828376 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2753 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392924.pdf [firstpage_image] =>[orig_patent_app_number] => 09828376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828376
Array for forming magnetoresistive random access memory with pseudo spin valve Apr 5, 2001 Issued
Array ( [id] => 1180327 [patent_doc_number] => 06751151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Ultra high-speed DDP-SRAM cache' [patent_app_type] => B2 [patent_app_number] => 09/827073 [patent_app_country] => US [patent_app_date] => 2001-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2790 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751151.pdf [firstpage_image] =>[orig_patent_app_number] => 09827073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/827073
Ultra high-speed DDP-SRAM cache Apr 4, 2001 Issued
Array ( [id] => 6893542 [patent_doc_number] => 20010015908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'STORAGE DEVICE WITH AN ERROR CORRECTION UNIT AND AN IMPROVED ARRANGEMENT FOR ACCESSING AND TRANSFERRING BLOCKS OF DATA STORED IN A NON-VOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => new [patent_app_number] => 09/824778 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12617 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015908.pdf [firstpage_image] =>[orig_patent_app_number] => 09824778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824778
Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory Apr 3, 2001 Issued
Array ( [id] => 1603875 [patent_doc_number] => 06434058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/817179 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6006 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434058.pdf [firstpage_image] =>[orig_patent_app_number] => 09817179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817179
Semiconductor integrated circuit Mar 26, 2001 Issued
Array ( [id] => 6338169 [patent_doc_number] => 20020034115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode' [patent_app_type] => new [patent_app_number] => 09/818876 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3345 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20020034115.pdf [firstpage_image] =>[orig_patent_app_number] => 09818876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818876
Semiconductor memory device having fixed CAS latency in normal operation and various CAS latencies in test mode Mar 26, 2001 Issued
Array ( [id] => 6884398 [patent_doc_number] => 20010038557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Circuit configuration for generating a reference voltage for reading a ferroelectric memory' [patent_app_type] => new [patent_app_number] => 09/817578 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4399 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20010038557.pdf [firstpage_image] =>[orig_patent_app_number] => 09817578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817578
Circuit configuration for generating a reference voltage for reading a ferroelectric memory Mar 25, 2001 Issued
Array ( [id] => 6888935 [patent_doc_number] => 20010024390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Semiconductor memory device and method of testing the same' [patent_app_type] => new [patent_app_number] => 09/812681 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9324 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024390.pdf [firstpage_image] =>[orig_patent_app_number] => 09812681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812681
Semiconductor memory device and method of testing the same Mar 20, 2001 Issued
Array ( [id] => 1463783 [patent_doc_number] => 06392951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-21 [patent_title] => 'Semiconductor storage device' [patent_app_type] => B2 [patent_app_number] => 09/813684 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 15632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392951.pdf [firstpage_image] =>[orig_patent_app_number] => 09813684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813684
Semiconductor storage device Mar 19, 2001 Issued
Array ( [id] => 6062025 [patent_doc_number] => 20020031041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ADJUSTING INTERNAL PARAMETER' [patent_app_type] => new [patent_app_number] => 09/811580 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9594 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031041.pdf [firstpage_image] =>[orig_patent_app_number] => 09811580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811580
Semiconductor memory device capable of adjusting internal parameter Mar 19, 2001 Issued
Array ( [id] => 678372 [patent_doc_number] => 07088604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Multi-bank memory' [patent_app_type] => utility [patent_app_number] => 09/809586 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2996 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088604.pdf [firstpage_image] =>[orig_patent_app_number] => 09809586 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809586
Multi-bank memory Mar 14, 2001 Issued
Array ( [id] => 5998443 [patent_doc_number] => 20020027801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/808181 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027801.pdf [firstpage_image] =>[orig_patent_app_number] => 09808181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808181
Semiconductor integrated circuit Mar 14, 2001 Issued
Array ( [id] => 5842243 [patent_doc_number] => 20020131297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Memory element, method for structuring a surface, and storage device' [patent_app_type] => new [patent_app_number] => 09/804984 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6067 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20020131297.pdf [firstpage_image] =>[orig_patent_app_number] => 09804984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804984
Memory element, method for structuring a surface, and storage device Mar 12, 2001 Issued
Array ( [id] => 7012491 [patent_doc_number] => 20010050367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Methods of reading and writing data from/ on semiconductor memory device, and method for driving the device' [patent_app_type] => new [patent_app_number] => 09/800478 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9274 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20010050367.pdf [firstpage_image] =>[orig_patent_app_number] => 09800478 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800478
Methods of reading and writing data from/ on semiconductor memory device, and method for driving the device Mar 7, 2001 Issued
Array ( [id] => 6338165 [patent_doc_number] => 20020034114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'REFRESH-FREE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => new [patent_app_number] => 09/797984 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 22436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20020034114.pdf [firstpage_image] =>[orig_patent_app_number] => 09797984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797984
Refresh-free semiconductor memory device Mar 4, 2001 Issued
Array ( [id] => 6901161 [patent_doc_number] => 20010022744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Semiconductor memory device having a page latch circuit and a test method thereof' [patent_app_type] => new [patent_app_number] => 09/794076 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8320 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022744.pdf [firstpage_image] =>[orig_patent_app_number] => 09794076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794076
Semiconductor memory device having a page latch circuit and a test method thereof Feb 27, 2001 Abandoned
Array ( [id] => 1179519 [patent_doc_number] => 06747474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Integrated circuit stubs in a point-to-point system' [patent_app_type] => B2 [patent_app_number] => 09/797480 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2592 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747474.pdf [firstpage_image] =>[orig_patent_app_number] => 09797480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797480
Integrated circuit stubs in a point-to-point system Feb 27, 2001 Issued
Array ( [id] => 1442648 [patent_doc_number] => 06496437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 09/795750 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12965 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496437.pdf [firstpage_image] =>[orig_patent_app_number] => 09795750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795750
Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory Feb 26, 2001 Issued
Array ( [id] => 1483002 [patent_doc_number] => 06452869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Address broadcasting to a paged memory device to eliminate access latency penalty' [patent_app_type] => B1 [patent_app_number] => 09/794478 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3509 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452869.pdf [firstpage_image] =>[orig_patent_app_number] => 09794478 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794478
Address broadcasting to a paged memory device to eliminate access latency penalty Feb 25, 2001 Issued
Array ( [id] => 1416742 [patent_doc_number] => 06538923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Staircase program verify for multi-level cell flash memory designs' [patent_app_type] => B1 [patent_app_number] => 09/794482 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 14 [patent_no_of_words] => 8713 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538923.pdf [firstpage_image] =>[orig_patent_app_number] => 09794482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794482
Staircase program verify for multi-level cell flash memory designs Feb 25, 2001 Issued
Array ( [id] => 1319125 [patent_doc_number] => 06614683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Ascending staircase read technique for a multilevel cell NAND flash memory device' [patent_app_type] => B1 [patent_app_number] => 09/794480 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5303 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614683.pdf [firstpage_image] =>[orig_patent_app_number] => 09794480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794480
Ascending staircase read technique for a multilevel cell NAND flash memory device Feb 25, 2001 Issued
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