Trong Q. Phan

Array ( [id] => 1342179 [patent_doc_number] => 06597621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Multi-bank semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/791778 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 14371 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597621.pdf [firstpage_image] =>[orig_patent_app_number] => 09791778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6139713 [patent_doc_number] => 20020001237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Non-volatile memory device with configurable row redundancy' [patent_app_type] => new [patent_app_number] => 09/785079 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001237.pdf [firstpage_image] =>[orig_patent_app_number] => 09785079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7635477 [patent_doc_number] => 06381185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method and a circuit architecture for testing an integrated circuit comprising a programmable, non-volatile memory' [patent_app_type] => B2 [patent_app_number] => 09/782969 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6035 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381185.pdf [firstpage_image] =>[orig_patent_app_number] => 09782969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1496412 [patent_doc_number] => 06343029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Charge shared match line differential generation for CAM' [patent_app_type] => B1 [patent_app_number] => 09/782576 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2767 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343029.pdf [firstpage_image] =>[orig_patent_app_number] => 09782576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1443067 [patent_doc_number] => 06335903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-01 [patent_title] => 'Memory system' [patent_app_type] => B2 [patent_app_number] => 09/778785 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6152 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335903.pdf [firstpage_image] =>[orig_patent_app_number] => 09778785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1511444 [patent_doc_number] => 06442098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'High performance multi-bank compact synchronous DRAM architecture' [patent_app_type] => B1 [patent_app_number] => 09/778382 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7161 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442098.pdf [firstpage_image] =>[orig_patent_app_number] => 09778382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1470077 [patent_doc_number] => 06459647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Split-bank architecture for high performance SDRAMs' [patent_app_type] => B1 [patent_app_number] => 09/778380 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5581 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459647.pdf [firstpage_image] =>[orig_patent_app_number] => 09778380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6155743 [patent_doc_number] => 20020145931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Method and apparatus for storing data in an integrated circuit' [patent_app_type] => new [patent_app_number] => 09/777180 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2665 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145931.pdf [firstpage_image] =>[orig_patent_app_number] => 09777180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7624495 [patent_doc_number] => 06724681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Asynchronously-resettable decoder with redundancy' [patent_app_type] => B2 [patent_app_number] => 09/775476 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 16986 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724681.pdf [firstpage_image] =>[orig_patent_app_number] => 09775476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1523384 [patent_doc_number] => 06414899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-02 [patent_title] => 'Limited swing driver circuit' [patent_app_type] => B2 [patent_app_number] => 09/775478 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 16528 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414899.pdf [firstpage_image] =>[orig_patent_app_number] => 09775478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1382684 [patent_doc_number] => 06563339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Multiple voltage supply switch' [patent_app_type] => B2 [patent_app_number] => 09/773284 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8017 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 35 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563339.pdf [firstpage_image] =>[orig_patent_app_number] => 09773284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6891629 [patent_doc_number] => 20010017791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Dynamic random access memory (DRAM) having ATD circuit' [patent_app_type] => new [patent_app_number] => 09/772079 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4285 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017791.pdf [firstpage_image] =>[orig_patent_app_number] => 09772079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1343960 [patent_doc_number] => 06590253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Memory cell with self-aligned floating gate and separate select gate, and fabrication process' [patent_app_type] => B2 [patent_app_number] => 09/768984 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 7178 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590253.pdf [firstpage_image] =>[orig_patent_app_number] => 09768984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6895701 [patent_doc_number] => 20010026491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration' [patent_app_type] => new [patent_app_number] => 09/767380 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3415 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026491.pdf [firstpage_image] =>[orig_patent_app_number] => 09767380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6223086 [patent_doc_number] => 20020003746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Memory address driver circuit' [patent_app_type] => new [patent_app_number] => 09/761880 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2075 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003746.pdf [firstpage_image] =>[orig_patent_app_number] => 09761880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1547000 [patent_doc_number] => 06373784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/764480 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373784.pdf [firstpage_image] =>[orig_patent_app_number] => 09764480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1449998 [patent_doc_number] => 06455392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-24 [patent_title] => 'Integrated resistor having aligned body and contact and method for forming the same' [patent_app_type] => B2 [patent_app_number] => 09/760178 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3759 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455392.pdf [firstpage_image] =>[orig_patent_app_number] => 09760178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6519905 [patent_doc_number] => 20020136054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Memory device with multi-level storage cells and apparatuses, systems and methods including same' [patent_app_type] => new [patent_app_number] => 09/758476 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3494 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20020136054.pdf [firstpage_image] =>[orig_patent_app_number] => 09758476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7040534 [patent_doc_number] => 20010005334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new-utility [patent_app_number] => 09/750882 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8506 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005334.pdf [firstpage_image] =>[orig_patent_app_number] => 09750882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1555934 [patent_doc_number] => 06349056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method and structure for efficient data verification operation for non-volatile memories' [patent_app_type] => B1 [patent_app_number] => 09/751178 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2765 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349056.pdf [firstpage_image] =>[orig_patent_app_number] => 09751178 [rel_patent_id] =>[rel_patent_doc_number] =>)