Trong Q Phan

Array ( [id] => 4358592 [patent_doc_number] => 06285576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Nonvolatile ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 9/653580 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9871 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285576.pdf [firstpage_image] =>[orig_patent_app_number] => 653580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327243 [patent_doc_number] => 06243290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/645878 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 65 [patent_no_of_words] => 28874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243290.pdf [firstpage_image] =>[orig_patent_app_number] => 645878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1564357 [patent_doc_number] => 06438066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system' [patent_app_type] => B1 [patent_app_number] => 09/641901 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 48 [patent_no_of_words] => 28346 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438066.pdf [firstpage_image] =>[orig_patent_app_number] => 09641901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1550340 [patent_doc_number] => 06445636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and system for hiding refreshes in a dynamic random access memory' [patent_app_type] => B1 [patent_app_number] => 09/641881 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4451 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445636.pdf [firstpage_image] =>[orig_patent_app_number] => 09641881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1423258 [patent_doc_number] => 06522181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Semiconductor memory apparatus which can easily attain reduction of access time' [patent_app_type] => B1 [patent_app_number] => 09/640180 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 8340 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522181.pdf [firstpage_image] =>[orig_patent_app_number] => 09640180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1406821 [patent_doc_number] => 06542000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Nonvolatile programmable logic devices' [patent_app_type] => B1 [patent_app_number] => 09/627576 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6034 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542000.pdf [firstpage_image] =>[orig_patent_app_number] => 09627576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4290816 [patent_doc_number] => 06282112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Network storage system' [patent_app_type] => 1 [patent_app_number] => 9/624349 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3893 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282112.pdf [firstpage_image] =>[orig_patent_app_number] => 624349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4262639 [patent_doc_number] => 06222761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method for minimizing program disturb in a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/617281 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7652 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222761.pdf [firstpage_image] =>[orig_patent_app_number] => 617281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305071 [patent_doc_number] => 06236595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Programming method for a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/617280 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7164 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236595.pdf [firstpage_image] =>[orig_patent_app_number] => 617280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4273604 [patent_doc_number] => 06259649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Semiconductor memory circuit layout capable of reducing the number of wires' [patent_app_type] => 1 [patent_app_number] => 9/617278 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1613 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259649.pdf [firstpage_image] =>[orig_patent_app_number] => 617278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420189 [patent_doc_number] => 06229756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Semiconductor memory device capable of preventing mis-operation due to load of column address line' [patent_app_type] => 1 [patent_app_number] => 9/616380 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3537 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229756.pdf [firstpage_image] =>[orig_patent_app_number] => 616380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417064 [patent_doc_number] => 06233198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'High density flash memory device with improved row decoding structure' [patent_app_type] => 1 [patent_app_number] => 9/615176 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3054 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233198.pdf [firstpage_image] =>[orig_patent_app_number] => 615176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326228 [patent_doc_number] => 06317362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/614778 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5655 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317362.pdf [firstpage_image] =>[orig_patent_app_number] => 614778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366964 [patent_doc_number] => 06292406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method and low-power circuits used to generate accurate boosted wordline voltage for flash memory core cells in read mode' [patent_app_type] => 1 [patent_app_number] => 9/609678 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5353 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292406.pdf [firstpage_image] =>[orig_patent_app_number] => 609678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1576694 [patent_doc_number] => 06469482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Inductive charge pump circuit for providing voltages useful for flash memory and other applications' [patent_app_type] => B1 [patent_app_number] => 09/607483 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6696 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469482.pdf [firstpage_image] =>[orig_patent_app_number] => 09607483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1199371 [patent_doc_number] => 06728161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Zero latency-zero bus turnaround synchronous flash memory' [patent_app_type] => B1 [patent_app_number] => 09/608580 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 13968 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728161.pdf [firstpage_image] =>[orig_patent_app_number] => 09608580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4341754 [patent_doc_number] => 06320782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor memory device and various systems mounting them' [patent_app_type] => 1 [patent_app_number] => 9/609058 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 378 [patent_no_of_words] => 66444 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320782.pdf [firstpage_image] =>[orig_patent_app_number] => 609058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1593595 [patent_doc_number] => 06483759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing' [patent_app_type] => B1 [patent_app_number] => 09/607788 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3657 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483759.pdf [firstpage_image] =>[orig_patent_app_number] => 09607788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4263059 [patent_doc_number] => 06222789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Sub word line driving circuit' [patent_app_type] => 1 [patent_app_number] => 9/607084 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2783 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222789.pdf [firstpage_image] =>[orig_patent_app_number] => 607084 [rel_patent_id] =>[rel_patent_doc_number] =>)