Search

Trong Q Phan

Examiner (ID: 15831, Phone: (571)272-1794 , Office: P/2825 )

Most Active Art Unit
2818
Art Unit(s)
2827, 2511, 2504, 2824, 2825, 2899, 2818
Total Applications
3077
Issued Applications
2717
Pending Applications
50
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1525662 [patent_doc_number] => 06353574 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Semiconductor memory device having pipe register operating at high speed' [patent_app_type] => B1 [patent_app_number] => 09/606240 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4728 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353574.pdf [firstpage_image] =>[orig_patent_app_number] => 09606240 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606240
Semiconductor memory device having pipe register operating at high speed Jun 27, 2000 Issued
Array ( [id] => 4426408 [patent_doc_number] => 06226209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/605446 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 14976 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226209.pdf [firstpage_image] =>[orig_patent_app_number] => 605446 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605446
Semiconductor memory device Jun 27, 2000 Issued
Array ( [id] => 1538464 [patent_doc_number] => 06337822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Write masking in a semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/604585 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4108 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337822.pdf [firstpage_image] =>[orig_patent_app_number] => 09604585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604585
Write masking in a semiconductor memory device Jun 26, 2000 Issued
Array ( [id] => 4285197 [patent_doc_number] => 06246636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Load signal generating circuit of a packet command driving type memory device' [patent_app_type] => 1 [patent_app_number] => 9/604476 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5441 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246636.pdf [firstpage_image] =>[orig_patent_app_number] => 604476 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604476
Load signal generating circuit of a packet command driving type memory device Jun 26, 2000 Issued
Array ( [id] => 4359111 [patent_doc_number] => 06285612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Reduced bit line equalization level sensing scheme' [patent_app_type] => 1 [patent_app_number] => 9/603683 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2735 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285612.pdf [firstpage_image] =>[orig_patent_app_number] => 603683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603683
Reduced bit line equalization level sensing scheme Jun 25, 2000 Issued
Array ( [id] => 1454340 [patent_doc_number] => 06456530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Nonvolatile memory device with hierarchical sector decoding' [patent_app_type] => B1 [patent_app_number] => 09/602680 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8525 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456530.pdf [firstpage_image] =>[orig_patent_app_number] => 09602680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/602680
Nonvolatile memory device with hierarchical sector decoding Jun 25, 2000 Issued
Array ( [id] => 1555062 [patent_doc_number] => 06400601 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/602178 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 13583 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400601.pdf [firstpage_image] =>[orig_patent_app_number] => 09602178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/602178
Nonvolatile semiconductor memory device Jun 21, 2000 Issued
Array ( [id] => 1216101 [patent_doc_number] => 06711058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Erase method for nonvolatile semiconductor storage device and row decoder circuit for fulfilling the method' [patent_app_type] => B1 [patent_app_number] => 09/598384 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 99 [patent_no_of_words] => 18682 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711058.pdf [firstpage_image] =>[orig_patent_app_number] => 09598384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598384
Erase method for nonvolatile semiconductor storage device and row decoder circuit for fulfilling the method Jun 20, 2000 Issued
Array ( [id] => 4284664 [patent_doc_number] => 06246601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus for using an inter-row configurable content addressable memory' [patent_app_type] => 1 [patent_app_number] => 9/594199 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 8970 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246601.pdf [firstpage_image] =>[orig_patent_app_number] => 594199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/594199
Method and apparatus for using an inter-row configurable content addressable memory Jun 13, 2000 Issued
Array ( [id] => 4373898 [patent_doc_number] => 06256228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for erasing nonvolatile semiconductor storage device capable of preventing erroneous reading' [patent_app_type] => 1 [patent_app_number] => 9/590378 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10939 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256228.pdf [firstpage_image] =>[orig_patent_app_number] => 590378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/590378
Method for erasing nonvolatile semiconductor storage device capable of preventing erroneous reading Jun 8, 2000 Issued
09/589748 Semiconductor memory device and method of operation thereof Jun 8, 2000 Abandoned
Array ( [id] => 1516566 [patent_doc_number] => 06420902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Field programmable logic arrays with transistors with vertical gates' [patent_app_type] => B1 [patent_app_number] => 09/583584 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 11243 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420902.pdf [firstpage_image] =>[orig_patent_app_number] => 09583584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583584
Field programmable logic arrays with transistors with vertical gates May 30, 2000 Issued
Array ( [id] => 4359008 [patent_doc_number] => 06285605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Integrated memory having redundant units of memory cells, and test method for the redundant units' [patent_app_type] => 1 [patent_app_number] => 9/580982 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3729 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285605.pdf [firstpage_image] =>[orig_patent_app_number] => 580982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/580982
Integrated memory having redundant units of memory cells, and test method for the redundant units May 29, 2000 Issued
Array ( [id] => 1555074 [patent_doc_number] => 06400605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method and system for pulse shaping in test and program modes' [patent_app_type] => B1 [patent_app_number] => 09/583319 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2711 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400605.pdf [firstpage_image] =>[orig_patent_app_number] => 09583319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583319
Method and system for pulse shaping in test and program modes May 29, 2000 Issued
Array ( [id] => 6868793 [patent_doc_number] => 20030081482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Semiconductor storage' [patent_app_type] => new [patent_app_number] => 09/577141 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20030081482.pdf [firstpage_image] =>[orig_patent_app_number] => 09577141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577141
Semiconductor storage May 23, 2000 Abandoned
Array ( [id] => 4419414 [patent_doc_number] => 06301178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Reduced cell voltage for memory device' [patent_app_type] => 1 [patent_app_number] => 9/575964 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6951 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301178.pdf [firstpage_image] =>[orig_patent_app_number] => 575964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/575964
Reduced cell voltage for memory device May 22, 2000 Issued
Array ( [id] => 1464361 [patent_doc_number] => 06351227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'A/D conversion offset error correction' [patent_app_type] => B1 [patent_app_number] => 09/576837 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 3337 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351227.pdf [firstpage_image] =>[orig_patent_app_number] => 09576837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576837
A/D conversion offset error correction May 21, 2000 Issued
Array ( [id] => 514709 [patent_doc_number] => 07199740 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-03 [patent_title] => 'Method and apparatus for use in switched capacitor systems' [patent_app_type] => utility [patent_app_number] => 09/575560 [patent_app_country] => US [patent_app_date] => 2000-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 58 [patent_no_of_words] => 17295 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/199/07199740.pdf [firstpage_image] =>[orig_patent_app_number] => 09575560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/575560
Method and apparatus for use in switched capacitor systems May 20, 2000 Issued
Array ( [id] => 994269 [patent_doc_number] => 06917321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-12 [patent_title] => 'Method and apparatus for use in switched capacitor systems' [patent_app_type] => utility [patent_app_number] => 09/575562 [patent_app_country] => US [patent_app_date] => 2000-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 58 [patent_no_of_words] => 17225 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917321.pdf [firstpage_image] =>[orig_patent_app_number] => 09575562 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/575562
Method and apparatus for use in switched capacitor systems May 20, 2000 Issued
Array ( [id] => 1038423 [patent_doc_number] => 06873278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Method and apparatus for use in switched capacitor systems' [patent_app_type] => utility [patent_app_number] => 09/575561 [patent_app_country] => US [patent_app_date] => 2000-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 58 [patent_no_of_words] => 17308 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873278.pdf [firstpage_image] =>[orig_patent_app_number] => 09575561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/575561
Method and apparatus for use in switched capacitor systems May 20, 2000 Issued
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