Trong Q Phan

Array ( [id] => 5950425 [patent_doc_number] => 20020006225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Encoding apparatus, decoding apparatus, encoding/decoding apparatus, encoding method and decoding method' [patent_app_type] => new [patent_app_number] => 09/547136 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 19335 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006225.pdf [firstpage_image] =>[orig_patent_app_number] => 09547136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1550269 [patent_doc_number] => 06445621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Dynamic data amplifier with built-in voltage level shifting' [patent_app_type] => B1 [patent_app_number] => 09/547384 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5321 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445621.pdf [firstpage_image] =>[orig_patent_app_number] => 09547384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291394 [patent_doc_number] => 06282150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/546178 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 12424 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282150.pdf [firstpage_image] =>[orig_patent_app_number] => 546178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1522813 [patent_doc_number] => 06414611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Reduction of aperture distortion in parallel A/D converters' [patent_app_type] => B1 [patent_app_number] => 09/545550 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1835 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414611.pdf [firstpage_image] =>[orig_patent_app_number] => 09545550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416398 [patent_doc_number] => 06272057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/545884 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8513 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272057.pdf [firstpage_image] =>[orig_patent_app_number] => 545884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4283482 [patent_doc_number] => 06307804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Semiconductor memory device capable of efficient memory cell select operation with reduced element count' [patent_app_type] => 1 [patent_app_number] => 9/543352 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 60 [patent_no_of_words] => 14461 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307804.pdf [firstpage_image] =>[orig_patent_app_number] => 543352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4286378 [patent_doc_number] => 06281819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Device for ENOB estimation for ADC\'s based on dynamic deviation and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/541859 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4232 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281819.pdf [firstpage_image] =>[orig_patent_app_number] => 541859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309391 [patent_doc_number] => 06181626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Self-timing circuit for semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/542078 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4464 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181626.pdf [firstpage_image] =>[orig_patent_app_number] => 542078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4393711 [patent_doc_number] => 06295225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Magnetic tunnel junction device having an intermediate layer' [patent_app_type] => 1 [patent_app_number] => 9/541079 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3329 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295225.pdf [firstpage_image] =>[orig_patent_app_number] => 541079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416910 [patent_doc_number] => 06233183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor memory device with high data access speed' [patent_app_type] => 1 [patent_app_number] => 9/539827 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4571 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233183.pdf [firstpage_image] =>[orig_patent_app_number] => 539827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1181811 [patent_doc_number] => 06744390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Analog to digital converter utilizing resolution enhancement' [patent_app_type] => B1 [patent_app_number] => 09/541460 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3070 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744390.pdf [firstpage_image] =>[orig_patent_app_number] => 09541460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426382 [patent_doc_number] => 06226199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Non-volatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/538525 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226199.pdf [firstpage_image] =>[orig_patent_app_number] => 538525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426412 [patent_doc_number] => 06226211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Merged memory-logic semiconductor device having a built-in self test circuit' [patent_app_type] => 1 [patent_app_number] => 9/539429 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2723 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226211.pdf [firstpage_image] =>[orig_patent_app_number] => 539429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4285074 [patent_doc_number] => 06246628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Semiconductor memory device having read/write amplifiers disposed for respective memory segments' [patent_app_type] => 1 [patent_app_number] => 9/537384 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3426 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246628.pdf [firstpage_image] =>[orig_patent_app_number] => 537384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354521 [patent_doc_number] => 06285305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Analog-to-digital converter circuit' [patent_app_type] => 1 [patent_app_number] => 9/538358 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2139 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285305.pdf [firstpage_image] =>[orig_patent_app_number] => 538358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4395408 [patent_doc_number] => 06278647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Semiconductor memory device having multi-bank and global data bus' [patent_app_type] => 1 [patent_app_number] => 9/537385 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2856 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278647.pdf [firstpage_image] =>[orig_patent_app_number] => 537385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1381275 [patent_doc_number] => 06574692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Apparatus and method of data processing through serial bus' [patent_app_type] => B1 [patent_app_number] => 09/536453 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2781 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574692.pdf [firstpage_image] =>[orig_patent_app_number] => 09536453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366752 [patent_doc_number] => 06292391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Isolation circuit and method for controlling discharge of high-voltage in a flash EEPROM' [patent_app_type] => 1 [patent_app_number] => 9/536387 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4272 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292391.pdf [firstpage_image] =>[orig_patent_app_number] => 536387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425612 [patent_doc_number] => 06195300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'CBR refresh control for the redundancy array' [patent_app_type] => 1 [patent_app_number] => 9/536185 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195300.pdf [firstpage_image] =>[orig_patent_app_number] => 536185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4286461 [patent_doc_number] => 06281825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Digital-to-analog converter' [patent_app_type] => 1 [patent_app_number] => 9/534955 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2880 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281825.pdf [firstpage_image] =>[orig_patent_app_number] => 534955 [rel_patent_id] =>[rel_patent_doc_number] =>)